Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996798
N. Chang, Yao-Wen Chang, I. Jiang
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout, optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and., wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulate to interconnect-driven floorplanning that considers not only the buffer-block planning but also wire-size planning.
{"title":"Formulae for performance optimization and their applications to interconnect-driven floorplanning","authors":"N. Chang, Yao-Wen Chang, I. Jiang","doi":"10.1109/ISQED.2002.996798","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996798","url":null,"abstract":"As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout, optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and., wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulate to interconnect-driven floorplanning that considers not only the buffer-block planning but also wire-size planning.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89600111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996764
A. Mezhiba, E. Friedman
The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties provide accurate and efficient estimates of the inductance of power grid structures with various dimensions.
{"title":"Inductive characteristics of power distribution grids in high speed integrated circuits","authors":"A. Mezhiba, E. Friedman","doi":"10.1109/ISQED.2002.996764","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996764","url":null,"abstract":"The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties provide accurate and efficient estimates of the inductance of power grid structures with various dimensions.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88460764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996695
Himanshu Kaul, D. Sylvester
We propose a new receiver to reduce the number of repeaters used in global wiring. The receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Using the TAGS receiver we can run a 15 mm line (180 nm node) at 800 MHz with no repeaters. The same line requires three repeaters with a traditional receiver and consumed more power and area. The TAGS receiver also outperforms a standard inverter at the 70 nm technology node. A noise analysis at the two technology nodes shows that the receiver maintains good functional noise immunity.
{"title":"Transition aware global signaling (TAGS)","authors":"Himanshu Kaul, D. Sylvester","doi":"10.1109/ISQED.2002.996695","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996695","url":null,"abstract":"We propose a new receiver to reduce the number of repeaters used in global wiring. The receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Using the TAGS receiver we can run a 15 mm line (180 nm node) at 800 MHz with no repeaters. The same line requires three repeaters with a traditional receiver and consumed more power and area. The TAGS receiver also outperforms a standard inverter at the 70 nm technology node. A noise analysis at the two technology nodes shows that the receiver maintains good functional noise immunity.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83388878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996757
G. Servel, D. Deschacht, Françoise Saliou, J. Mattei, F. Huret
With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.
{"title":"Impact of low-k on crosstalk [deep sub-micron technologies]","authors":"G. Servel, D. Deschacht, Françoise Saliou, J. Mattei, F. Huret","doi":"10.1109/ISQED.2002.996757","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996757","url":null,"abstract":"With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89881288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996713
M. Kocher, G. Rappitsch
Presents a statistical method to determine the variation of the production process of MOS transistors by finding the wafers that have parameter values on the boundary of the distribution. For the selection of the wafers a location depth method is used. Since it would be too time-consuming to determine the SPICE parameters for all the wafers and compute the boundary wafers in the SPICE domain, we use a different approach. We compute the boundary wafers based on production control parameters and then we transform the production control parameter values to SPICE parameter values. With the SPICE parameter values obtained in this way the circuit simulation is performed and since we use the data of the boundary wafers, we cover the variation of the production process within a certain time period. The applied scheme proves to describe the performance variation of analog/mixed-signal designs very accurately with a small number of simulations. For validation purposes circuit simulations and measurements of benchmark circuits are compared. The statistical methods can easily be integrated into a mixed-signal design environment.
{"title":"Statistical methods for the determination of process corners","authors":"M. Kocher, G. Rappitsch","doi":"10.1109/ISQED.2002.996713","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996713","url":null,"abstract":"Presents a statistical method to determine the variation of the production process of MOS transistors by finding the wafers that have parameter values on the boundary of the distribution. For the selection of the wafers a location depth method is used. Since it would be too time-consuming to determine the SPICE parameters for all the wafers and compute the boundary wafers in the SPICE domain, we use a different approach. We compute the boundary wafers based on production control parameters and then we transform the production control parameter values to SPICE parameter values. With the SPICE parameter values obtained in this way the circuit simulation is performed and since we use the data of the boundary wafers, we cover the variation of the production process within a certain time period. The applied scheme proves to describe the performance variation of analog/mixed-signal designs very accurately with a small number of simulations. For validation purposes circuit simulations and measurements of benchmark circuits are compared. The statistical methods can easily be integrated into a mixed-signal design environment.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82359691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996796
O. Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. This paper focuses on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
{"title":"Timing and design closure in physical design flows","authors":"O. Coudert","doi":"10.1109/ISQED.2002.996796","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996796","url":null,"abstract":"A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. This paper focuses on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76261235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996737
Aiqun Cao, N. Sirisantana, Cheng-Kok Koh, K. Roy
Skewed logic circuits with a selective clocking scheme have performance comparable to that of Domino logic, but consume much lower power. Unlike Domino, the reconvergent path problem in skewed logic circuits may be overcome without logic duplication due to the static nature of skewed logic. In this paper, we propose a novel approach that alleviates the need for logic duplication when dealing with reconvergent paths in skewed logic circuits. We also propose a dynamic programming-based heuristic to determine a low-power clocking scheme for skewed logic circuits. Experimental results show that 32% of gates in a skewed logic circuit are duplicated, whereas 69% of gates in a Domino logic circuit are duplicated. The total power saving of skewed logic over Domino logic is 32.6% on average.
{"title":"Synthesis of selectively clocked skewed logic circuits","authors":"Aiqun Cao, N. Sirisantana, Cheng-Kok Koh, K. Roy","doi":"10.1109/ISQED.2002.996737","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996737","url":null,"abstract":"Skewed logic circuits with a selective clocking scheme have performance comparable to that of Domino logic, but consume much lower power. Unlike Domino, the reconvergent path problem in skewed logic circuits may be overcome without logic duplication due to the static nature of skewed logic. In this paper, we propose a novel approach that alleviates the need for logic duplication when dealing with reconvergent paths in skewed logic circuits. We also propose a dynamic programming-based heuristic to determine a low-power clocking scheme for skewed logic circuits. Experimental results show that 32% of gates in a skewed logic circuit are duplicated, whereas 69% of gates in a Domino logic circuit are duplicated. The total power saving of skewed logic over Domino logic is 32.6% on average.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74758947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996704
R. Aitken
Voltage stress testing has long been used as a reliability screen. Significant effort has been devoted in the reliability physics literature to setting of stress voltages. Chang and McCluskey formalized the test aspects of voltage stressing in their works on "SHOVE (SHort VOltage Elevation)" testing. Their work deals with 3.3V and 5V technologies where Fowler-Nordheim tunneling is dominant and suggests a stress energy of about 6MV/cm. In current generation technologies, Fowler-Nordheim tunneling is replaced by standard tunneling currents and operating energies are in the suggested stress range (e.g. 1.2V power supply with a 20/spl Aring/ oxide is 6MV/cm). Modified methods are developed to support this new situation, and a rest generation technique is introduced that enables substantial reduction in the number of stress vectors.
电压应力测试长期以来一直被用作可靠性测试。可靠性物理文献对应力电压的设置进行了大量的研究。Chang和McCluskey在他们关于“push (SHort voltage Elevation)”测试的著作中正式定义了电压应力的测试方面。他们的工作涉及3.3V和5V技术，其中Fowler-Nordheim隧穿占主导地位，并表明应力能约为6MV/cm。在当前的发电技术中，Fowler-Nordheim隧道被标准隧道电流取代，工作能量在建议的应力范围内(例如，1.2V电源与20/spl的电弧/氧化物为6MV/cm)。为了支持这种新情况，开发了改进的方法，并引入了一种休息生成技术，可以大幅减少应力向量的数量。
{"title":"Test generation and fault modeling for stress testing","authors":"R. Aitken","doi":"10.1109/ISQED.2002.996704","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996704","url":null,"abstract":"Voltage stress testing has long been used as a reliability screen. Significant effort has been devoted in the reliability physics literature to setting of stress voltages. Chang and McCluskey formalized the test aspects of voltage stressing in their works on \"SHOVE (SHort VOltage Elevation)\" testing. Their work deals with 3.3V and 5V technologies where Fowler-Nordheim tunneling is dominant and suggests a stress energy of about 6MV/cm. In current generation technologies, Fowler-Nordheim tunneling is replaced by standard tunneling currents and operating energies are in the suggested stress range (e.g. 1.2V power supply with a 20/spl Aring/ oxide is 6MV/cm). Modified methods are developed to support this new situation, and a rest generation technique is introduced that enables substantial reduction in the number of stress vectors.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73885644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996752
K. Jayaraman, V. Vedula, J. Abraham
With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor's instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.
{"title":"Native mode functional self-test generation for Systems-on-Chip","authors":"K. Jayaraman, V. Vedula, J. Abraham","doi":"10.1109/ISQED.2002.996752","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996752","url":null,"abstract":"With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor's instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91532897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996797
C. Lim, W. R. Daasch, George Z. N. Cai
A thermal-aware technique is proposed to minimize the performance impact when thermal/power control mechanism is triggered. This technique, called thermal-aware microprocessor (TAM), uses on-chip thermal sensors to detect hot-spots within the microprocessor die. There is a secondary pipeline within the core. It is architecturally simple with ultra low power implementation. This secondary pipeline has two main functions: 1. thermal relieve; 2. ultra low power implementation for certain mobile environment (such as any where any time email connect function). When temperature exceeds a given threshold, the core superscalar pipelines are clock-gated while a secondary in-order pipeline is engaged. Since the secondary pipeline consumes much less power, it will have a much lower temperature, and therefore, it will provide a temporary thermal relieve to the core pipelines when the thermal/power mechanism is triggered. This relief reduces energy loss due to leakage, prevents overheating to improve product reliability, and eases cost for thermal solutions. The TAM can also combine with other low power techniques such voltage scaling to achieve ultra low power.
{"title":"A thermal-aware superscalar microprocessor","authors":"C. Lim, W. R. Daasch, George Z. N. Cai","doi":"10.1109/ISQED.2002.996797","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996797","url":null,"abstract":"A thermal-aware technique is proposed to minimize the performance impact when thermal/power control mechanism is triggered. This technique, called thermal-aware microprocessor (TAM), uses on-chip thermal sensors to detect hot-spots within the microprocessor die. There is a secondary pipeline within the core. It is architecturally simple with ultra low power implementation. This secondary pipeline has two main functions: 1. thermal relieve; 2. ultra low power implementation for certain mobile environment (such as any where any time email connect function). When temperature exceeds a given threshold, the core superscalar pipelines are clock-gated while a secondary in-order pipeline is engaged. Since the secondary pipeline consumes much less power, it will have a much lower temperature, and therefore, it will provide a temporary thermal relieve to the core pipelines when the thermal/power mechanism is triggered. This relief reduces energy loss due to leakage, prevents overheating to improve product reliability, and eases cost for thermal solutions. The TAM can also combine with other low power techniques such voltage scaling to achieve ultra low power.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86797922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：