Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996788
G. Cho, Tom Chen
We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 /spl mu/m CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.
提出了一种新的基于遗传搜索的混合通管逻辑与静态CMOS逻辑综合方法。提出的合成方法首先使用bdd搜索逻辑结构与一组预定义的PTL/CMOS逻辑门之间的可能匹配。我们的方法的独特贡献是使用遗传算法来确定基于面积和功率的PTL和静态单元的最佳混合。我们的实验结果表明，在0.25 /spl μ l /m CMOS工艺下，采用所提出的混合PTL/CMOS合成方法合成的电路在延迟或功耗方面优于静态电路。采用该方法的ISCAS85和MCNC91基准电路的平均面积、功耗和功耗延迟积分别比静态电路高25%、40%和45%。
{"title":"Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications","authors":"G. Cho, Tom Chen","doi":"10.1109/ISQED.2002.996788","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996788","url":null,"abstract":"We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 /spl mu/m CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86904598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996775
R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama
A study of the future trends in low-power System-on-Chip (SoC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm/sup 2/ using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SoC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.
{"title":"Trends in low power digital system-on-chip designs","authors":"R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama","doi":"10.1109/ISQED.2002.996775","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996775","url":null,"abstract":"A study of the future trends in low-power System-on-Chip (SoC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm/sup 2/ using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SoC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89983536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996724
K. Shimazaki, S. Hirano, H. Tsujikawa
The EMI noise of LSI has become more significant factor for LSI reliability. The result of a transistor-level simulator was not compared sufficiently with measurement and needs the final layout. This paper shows an EMI-noise analysis method at the early stage of the LSI design. The spectrum of the power supply current and the frequency response of the LSI estimated impedance are merged analytically at high speed. The current can be calculated at high speed by a gate level simulator with a triangle model. The experimental results show that our method has a high accuracy that is correlated with measurement results. Furthermore, the estimation method of the LSI impedance enables EMI noise prediction at the early stage of LSI design. The information obtained from our method can also help designers to improve LSI and electronic systems design quality.
{"title":"An EMI-noise analysis on LSI design with impedance estimation","authors":"K. Shimazaki, S. Hirano, H. Tsujikawa","doi":"10.1109/ISQED.2002.996724","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996724","url":null,"abstract":"The EMI noise of LSI has become more significant factor for LSI reliability. The result of a transistor-level simulator was not compared sufficiently with measurement and needs the final layout. This paper shows an EMI-noise analysis method at the early stage of the LSI design. The spectrum of the power supply current and the frequency response of the LSI estimated impedance are merged analytically at high speed. The current can be calculated at high speed by a gate level simulator with a triangle model. The experimental results show that our method has a high accuracy that is correlated with measurement results. Furthermore, the estimation method of the LSI impedance enables EMI noise prediction at the early stage of LSI design. The information obtained from our method can also help designers to improve LSI and electronic systems design quality.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89150607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996734
Chan Wu
The microwave III-V semiconductor IC technology (primarily GaAs) has emerged as a powerful enabling technology for wireless and optical communications in the past 5 years. It has been dominating, or making substantial penetration into, the market for handset power amplifiers and switches, advanced wireless LAN RF front-ends and various other key RF components for broadband wireless, wireless infrastructure, satellite telecommunications, high data rate fiber optical communications and automotive radar applications. The microwave III-V semiconductor IC industry has grown dramatically in the past 2-3 years. It is worth noting that the majority of the recently formed GaAs fabs are located in Taiwan. Their intent is to provide pure-play foundry services following the silicon foundry business model developed by TSMC and UMC. In this presentation, we discuss the key components of III-V microwave transistors (HBT, pHEMT and MESFET etc.) and their RFICs/MMICs, their electrical performance, major applications, market status, trends and opportunities. We define the current status for the global III-V semiconductor industry, the rapidly growing GaAs MMIC fab industry in Taiwan and its advantages for providing a one-stop, total solution for wireless and optical communication components customers.
{"title":"Microwave III-V semiconductors for telecommunications and prospective of the III-V industry","authors":"Chan Wu","doi":"10.1109/ISQED.2002.996734","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996734","url":null,"abstract":"The microwave III-V semiconductor IC technology (primarily GaAs) has emerged as a powerful enabling technology for wireless and optical communications in the past 5 years. It has been dominating, or making substantial penetration into, the market for handset power amplifiers and switches, advanced wireless LAN RF front-ends and various other key RF components for broadband wireless, wireless infrastructure, satellite telecommunications, high data rate fiber optical communications and automotive radar applications. The microwave III-V semiconductor IC industry has grown dramatically in the past 2-3 years. It is worth noting that the majority of the recently formed GaAs fabs are located in Taiwan. Their intent is to provide pure-play foundry services following the silicon foundry business model developed by TSMC and UMC. In this presentation, we discuss the key components of III-V microwave transistors (HBT, pHEMT and MESFET etc.) and their RFICs/MMICs, their electrical performance, major applications, market status, trends and opportunities. We define the current status for the global III-V semiconductor industry, the rapidly growing GaAs MMIC fab industry in Taiwan and its advantages for providing a one-stop, total solution for wireless and optical communication components customers.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76562334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996696
Daniel Moritz
Design and timing closure are critical issues in modern design flows. Industry common library formats like .lib, CLF and TLF do not provide a means to embed arbitrary delay information and complex interconnect algorithms. Designers and silicon providers are at the mercy of these restrictions. Algorithms are applied to characterization data and proprietary interconnect analysis modules to minimize the error when mapping into these formats. The result is that numerous errors creep in to the tools that employ these formats. Often, these inaccuracies force unnecessary design iterations, technology guard banding, and finger pointing between the tool and library providers. With interconnect delay dominating path timing, it is more critical than ever to move past the text based library formats and to an API based solution that provides a way to embed interconnect analysis in the technology models. The Open Library Architecture addresses these issues by implementing an open C API. This API allows the library vendor to implement arbitrary data structures and algorithms. The same OLA module is employed consistently throughout the design flow which eliminates the loops which lead to inaccurate library mapping algorithms.
{"title":"Using the Open Library Architecture (OLA) open source API in heterogeneous design flows","authors":"Daniel Moritz","doi":"10.1109/ISQED.2002.996696","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996696","url":null,"abstract":"Design and timing closure are critical issues in modern design flows. Industry common library formats like .lib, CLF and TLF do not provide a means to embed arbitrary delay information and complex interconnect algorithms. Designers and silicon providers are at the mercy of these restrictions. Algorithms are applied to characterization data and proprietary interconnect analysis modules to minimize the error when mapping into these formats. The result is that numerous errors creep in to the tools that employ these formats. Often, these inaccuracies force unnecessary design iterations, technology guard banding, and finger pointing between the tool and library providers. With interconnect delay dominating path timing, it is more critical than ever to move past the text based library formats and to an API based solution that provides a way to embed interconnect analysis in the technology models. The Open Library Architecture addresses these issues by implementing an open C API. This API allows the library vendor to implement arbitrary data structures and algorithms. The same OLA module is employed consistently throughout the design flow which eliminates the loops which lead to inaccurate library mapping algorithms.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80539322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996727
D. Maynard
Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturability (DFM) has become a popular industry term, yet many chip designers are uncertain where to start and what to implement. The semiconductor manufacturer possesses knowledge or suspicions of potential barriers and improvement opportunities. This information must be proactively fed forward to the design shops, which must also budget resources and time to address these items. This presentation describes how this process works, illustrated with examples from IBM Microelectronics' Vermont facility. Before focusing on productivity optimization, a recommended set of metrics is identified, and the concept of physical design characterization is overviewed. Past and existing designs provide excellent historical insight into a large number of issues that are often independent of technology node. While robust technology development objectives strive to minimize the potential manufacturing stumbling blocks, competitive pressures will balance these with other constraints. Ultimately, it is decisions made by a designer that will determine the level of productivity achievable. Much of this presentation is devoted to describing a number of these decisions. In addition, the manufacturer may deploy complex algorithms to adjust the design to process constraints. Another, but more costly solution is for the manufacturer to tailor the process to a specific product, compensating for identified product-technology gaps. Lastly, this presentation ties these concepts together into a recommended business process.
{"title":"Productivity optimization techniques for the proactive semiconductor manufacturer","authors":"D. Maynard","doi":"10.1109/ISQED.2002.996727","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996727","url":null,"abstract":"Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturability (DFM) has become a popular industry term, yet many chip designers are uncertain where to start and what to implement. The semiconductor manufacturer possesses knowledge or suspicions of potential barriers and improvement opportunities. This information must be proactively fed forward to the design shops, which must also budget resources and time to address these items. This presentation describes how this process works, illustrated with examples from IBM Microelectronics' Vermont facility. Before focusing on productivity optimization, a recommended set of metrics is identified, and the concept of physical design characterization is overviewed. Past and existing designs provide excellent historical insight into a large number of issues that are often independent of technology node. While robust technology development objectives strive to minimize the potential manufacturing stumbling blocks, competitive pressures will balance these with other constraints. Ultimately, it is decisions made by a designer that will determine the level of productivity achievable. Much of this presentation is devoted to describing a number of these decisions. In addition, the manufacturer may deploy complex algorithms to adjust the design to process constraints. Another, but more costly solution is for the manufacturer to tailor the process to a specific product, compensating for identified product-technology gaps. Lastly, this presentation ties these concepts together into a recommended business process.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81144936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996768
M. Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo
A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique, can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased /spl sim/65% by this substrate-triggered design.
{"title":"ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process","authors":"M. Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo","doi":"10.1109/ISQED.2002.996768","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996768","url":null,"abstract":"A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique, can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased /spl sim/65% by this substrate-triggered design.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73877629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996699
G. Ben-Yaacov, P. Suratkar, M. Holliday, K. Bartleson
In the fast-paced electronics market, design engineers face incredible challenges to keep up with increasing technology complexity and time-to market pressures. Under these challenges, design engineers have been saying that quality issues with their EDA software tools cost them dearly in lost productivity and in missing tight deadlines. Therefore, improving the quality of EDA software tools and processes is essential to the designers' success. Our paper describes a proven methodology for implementation of an effective quality management system (QMS) for driving quality improvements in the EDA industry. The paper provide real-life examples of how this quality management system contributed to improvements in the quality of many EDA software tools that were developed by a leading EDA tool supplier. The positive results of the software process improvement effort demonstrated that investing in quality does pay. Effective implementation of the quality management system described in this paper has reduced software bugs and defects, produced improvements in meeting commitments, and contributed to the overall increase in customer satisfaction.
{"title":"Advancing quality of EDA software","authors":"G. Ben-Yaacov, P. Suratkar, M. Holliday, K. Bartleson","doi":"10.1109/ISQED.2002.996699","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996699","url":null,"abstract":"In the fast-paced electronics market, design engineers face incredible challenges to keep up with increasing technology complexity and time-to market pressures. Under these challenges, design engineers have been saying that quality issues with their EDA software tools cost them dearly in lost productivity and in missing tight deadlines. Therefore, improving the quality of EDA software tools and processes is essential to the designers' success. Our paper describes a proven methodology for implementation of an effective quality management system (QMS) for driving quality improvements in the EDA industry. The paper provide real-life examples of how this quality management system contributed to improvements in the quality of many EDA software tools that were developed by a leading EDA tool supplier. The positive results of the software process improvement effort demonstrated that investing in quality does pay. Effective implementation of the quality management system described in this paper has reduced software bugs and defects, produced improvements in meeting commitments, and contributed to the overall increase in customer satisfaction.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76392878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996780
N. Q. Trung, A. Kokoszka, K. Siekierska, A. Pawlak, D. Obrebski, Norbert Lugowski
The paper presents a new approach towards large system design in distributed teams based on a workflow technology. The techniques applied introduce interoperability among design tools across computing platforms and organization borders. They result in an improved quality of wide area engineering collaboration. After a short discussion about selected aspects of the applied workflow technology from an electronic design engineers' perspective, an Internet-based distributed design process of IP components with emphasis on specific elements of microprocessor designs is introduced. As an example, we present a workflow that enables integration and interoperability of selected IP design tasks, represented as parallel and serial sets of the workflow activities. The workflows that were employed in the design process had been developed for the purpose of design task integration in the pan-European project E-Colleg. They can be effectively adopted by distributed teams working on multiple sites, multiple platforms for remote project management.
{"title":"Organization of a microprocessor design process using Internet-based interoperable workflows","authors":"N. Q. Trung, A. Kokoszka, K. Siekierska, A. Pawlak, D. Obrebski, Norbert Lugowski","doi":"10.1109/ISQED.2002.996780","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996780","url":null,"abstract":"The paper presents a new approach towards large system design in distributed teams based on a workflow technology. The techniques applied introduce interoperability among design tools across computing platforms and organization borders. They result in an improved quality of wide area engineering collaboration. After a short discussion about selected aspects of the applied workflow technology from an electronic design engineers' perspective, an Internet-based distributed design process of IP components with emphasis on specific elements of microprocessor designs is introduced. As an example, we present a workflow that enables integration and interoperability of selected IP design tasks, represented as parallel and serial sets of the workflow activities. The workflows that were employed in the design process had been developed for the purpose of design task integration in the pan-European project E-Colleg. They can be effectively adopted by distributed teams working on multiple sites, multiple platforms for remote project management.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83714465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996794
A. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P. Fluckiger, G. Racine
A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.
{"title":"Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture","authors":"A. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P. Fluckiger, G. Racine","doi":"10.1109/ISQED.2002.996794","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996794","url":null,"abstract":"A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80461351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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