Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996698
R. Seepold, N. M. Madrid, A. Vörg, W. Rosenstiel, M. Radetzki, P. Neumann, Jürgen Haase
The application and development of reusable components (intellectual property, IP) has become a regular part of modern design practices. The IP provider on one side and the IP integrator (user) on the other may be in the same company or separate participants in the microelectronic design market. In both cases, the transfer of IP remains a complex and time-consuming task. The qualification of IP gains a significant relevance for successful application and transfer of IP. This paper proposes an IP qualification methodology for an automated quality check that also incorporates current standards. Through embedding of the new concept into the regular design flow, IP transfer comes closer to an easy mix and match of virtual components. The presented approach has been validated during an industrial case study.
{"title":"A qualification platform for design reuse","authors":"R. Seepold, N. M. Madrid, A. Vörg, W. Rosenstiel, M. Radetzki, P. Neumann, Jürgen Haase","doi":"10.1109/ISQED.2002.996698","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996698","url":null,"abstract":"The application and development of reusable components (intellectual property, IP) has become a regular part of modern design practices. The IP provider on one side and the IP integrator (user) on the other may be in the same company or separate participants in the microelectronic design market. In both cases, the transfer of IP remains a complex and time-consuming task. The qualification of IP gains a significant relevance for successful application and transfer of IP. This paper proposes an IP qualification methodology for an automated quality check that also incorporates current standards. Through embedding of the new concept into the regular design flow, IP transfer comes closer to an easy mix and match of virtual components. The presented approach has been validated during an industrial case study.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91508971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996779
J. R. Sendra, J. Pino, A. Hernández, Javier Hernández, J. Aguilera, A. Garcia-Alonso, A. Núñez
In this work we propose new equivalent circuit models for integrated inductors based on the conventional lumped element model. Automatic tools to assist the designers in selecting and automatically laying-out integrated inductors are also reported. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We demonstrate the capacity of the proposed models to accurately predict the integrated inductor behavior in a wider frequency range than the conventional model. Our equations are coded in a set of tools that requests the desired inductance value at a determined frequency and gives back the geometry of the better inductors available in a particular technology.
{"title":"Integrated inductors modeling and tools for automatic selection and layout generation","authors":"J. R. Sendra, J. Pino, A. Hernández, Javier Hernández, J. Aguilera, A. Garcia-Alonso, A. Núñez","doi":"10.1109/ISQED.2002.996779","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996779","url":null,"abstract":"In this work we propose new equivalent circuit models for integrated inductors based on the conventional lumped element model. Automatic tools to assist the designers in selecting and automatically laying-out integrated inductors are also reported. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We demonstrate the capacity of the proposed models to accurately predict the integrated inductor behavior in a wider frequency range than the conventional model. Our equations are coded in a set of tools that requests the desired inductance value at a determined frequency and gives back the geometry of the better inductors available in a particular technology.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86785721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996688
V. Jandhyala, Yong Wang, D. Gope, C. Shi
The partial-element-equivalent-circuit (PEEC) approach is an effective method to convert three-dimensional on-chip multiconductor structures to circuit-level descriptions. In this paper, a triangular-mesh-based PEEC approach is described, wherein the surfaces of arbitrarily-shaped conducting structures are represented by triangular mesh tesselations. A coupled EM-circuit formulation is obtained through the separation of the scalar, vector, and ohmic potential interactions between pairs of triangular edges-based basis functions. The overall approach can be interpreted as a SPICE-free, surface-only version of PEEC method and is especially useful for on-chip signal integrity analysis of systems-on-chip layout where components with irregular shapes are common.
{"title":"Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures using triangular meshes","authors":"V. Jandhyala, Yong Wang, D. Gope, C. Shi","doi":"10.1109/ISQED.2002.996688","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996688","url":null,"abstract":"The partial-element-equivalent-circuit (PEEC) approach is an effective method to convert three-dimensional on-chip multiconductor structures to circuit-level descriptions. In this paper, a triangular-mesh-based PEEC approach is described, wherein the surfaces of arbitrarily-shaped conducting structures are represented by triangular mesh tesselations. A coupled EM-circuit formulation is obtained through the separation of the scalar, vector, and ohmic potential interactions between pairs of triangular edges-based basis functions. The overall approach can be interpreted as a SPICE-free, surface-only version of PEEC method and is especially useful for on-chip signal integrity analysis of systems-on-chip layout where components with irregular shapes are common.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84183327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996739
Bok-Gue Park, Koon-Shik Cho, Jun-Dong Cho
HMM-based algorithms have been successfully applied to speech recognition since HMM provides a robust modeling capability of various speech signals and maintains high recognition accuracy. Viterbi scoring that searches the best matching word by comparing input utterance with reference speech models is a major task in HMM-based speech recognition. However, due to its operation complexity, Viterbi scoring is a significant source of power and computation when it is implemented by a dedicated VLSI architecture. This paper proposes a noble low power VLSI architecture of Viterbi scorer using modified Viterbi scoring procedure and precomputing logic. This method reduced power consumption by 20% and 27% for 100 and 400 candidate word recognition, respectively, compared with a conventional architecture at a cost of at most 12% increase in area due to additional control logics. As the device shrinks, power consumption becomes more significant than chip area.
{"title":"Low power VLSI architecture of Viterbi scorer for HMM-based isolated word recognition","authors":"Bok-Gue Park, Koon-Shik Cho, Jun-Dong Cho","doi":"10.1109/ISQED.2002.996739","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996739","url":null,"abstract":"HMM-based algorithms have been successfully applied to speech recognition since HMM provides a robust modeling capability of various speech signals and maintains high recognition accuracy. Viterbi scoring that searches the best matching word by comparing input utterance with reference speech models is a major task in HMM-based speech recognition. However, due to its operation complexity, Viterbi scoring is a significant source of power and computation when it is implemented by a dedicated VLSI architecture. This paper proposes a noble low power VLSI architecture of Viterbi scorer using modified Viterbi scoring procedure and precomputing logic. This method reduced power consumption by 20% and 27% for 100 and 400 candidate word recognition, respectively, compared with a conventional architecture at a cost of at most 12% increase in area due to additional control logics. As the device shrinks, power consumption becomes more significant than chip area.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86032046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-01-01DOI: 10.1109/ISQED.2002.996564
The following topics are dealt with: interconnect extraction and modeling; design for process variations; design issues for power and noise management; low power design techniques; quality and interoperability of EDA tools; power, signal and EMI analysis and optimization; verification in achieving design quality; advanced device technology issues in circuit design; design for test; methods and metrics for design quality; signal integrity; design, planning and closure.
{"title":"Proceedings International Symposium on Quality Electronic Design","authors":"","doi":"10.1109/ISQED.2002.996564","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996564","url":null,"abstract":"The following topics are dealt with: interconnect extraction and modeling; design for process variations; design issues for power and noise management; low power design techniques; quality and interoperability of EDA tools; power, signal and EMI analysis and optimization; verification in achieving design quality; advanced device technology issues in circuit design; design for test; methods and metrics for design quality; signal integrity; design, planning and closure.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90122522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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