Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996785
A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, C. Oh
High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Since the problem has been shown to be NP-hard in general, exact solutions to this problem are not possible. In this paper, we therefore propose a new heuristic to eliminate false noise failures based on the resolution method. It is shown that multi-variable logic relations can be computed directly from a transistor level description. Based on these generated logic relations, a characteristic ROBDD for a signal net and its neighboring nets is constructed. This ROBDD is then used to determine the set of neighboring nets that result in the maximum realizable noise on the net. The proposed approach was implemented and tested on industrial circuits. The results demonstrate the effectiveness of the approach to eliminate false noise failures.
{"title":"False-noise analysis using resolution method","authors":"A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, C. Oh","doi":"10.1109/ISQED.2002.996785","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996785","url":null,"abstract":"High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Since the problem has been shown to be NP-hard in general, exact solutions to this problem are not possible. In this paper, we therefore propose a new heuristic to eliminate false noise failures based on the resolution method. It is shown that multi-variable logic relations can be computed directly from a transistor level description. Based on these generated logic relations, a characteristic ROBDD for a signal net and its neighboring nets is constructed. This ROBDD is then used to determine the set of neighboring nets that result in the maximum realizable noise on the net. The proposed approach was implemented and tested on industrial circuits. The results demonstrate the effectiveness of the approach to eliminate false noise failures.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72635082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996719
P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, B. Haroun
The combination of high operating frequencies and low-power requirements for DSP cores targeted towards mobile applications makes clock synthesis and phase synchronization for these devices very challenging. These constraints make all-digital solutions (digital PLLs and DLLs) an attractive option (Dunning et al, 1995; Fried, 1996; Minami et al, 2000). This paper describes a digital delay-line architecture that can be used for these applications in a 0.11 /spl mu/m (silicon gate length) CMOS technology. Process variability and sensitivities increase at these geometries and it is difficult to meet target specifications across the entire spread of variations in process, voltages and temperatures (PVT corners). The design methodology presented in this paper minimizes these sensitivities.
针对移动应用的DSP内核的高工作频率和低功耗要求的结合使得这些设备的时钟合成和相位同步非常具有挑战性。这些限制使得全数字解决方案(数字锁相环和dll)成为一个有吸引力的选择(Dunning等人，1995;炸,1996;Minami et al .， 2000)。本文介绍了一种可用于这些应用的0.11 /spl mu/m(硅栅长度)CMOS技术的数字延迟线架构。在这些几何形状上，工艺可变性和灵敏度增加，并且很难在工艺、电压和温度(PVT角)的整个变化范围内满足目标规格。本文提出的设计方法最大限度地减少了这些敏感性。
{"title":"A robust digital delay line architecture in a 0.13 /spl mu/m CMOS technology node for reduced design and process sensitivities","authors":"P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, B. Haroun","doi":"10.1109/ISQED.2002.996719","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996719","url":null,"abstract":"The combination of high operating frequencies and low-power requirements for DSP cores targeted towards mobile applications makes clock synthesis and phase synchronization for these devices very challenging. These constraints make all-digital solutions (digital PLLs and DLLs) an attractive option (Dunning et al, 1995; Fried, 1996; Minami et al, 2000). This paper describes a digital delay-line architecture that can be used for these applications in a 0.11 /spl mu/m (silicon gate length) CMOS technology. Process variability and sensitivities increase at these geometries and it is difficult to meet target specifications across the entire spread of variations in process, voltages and temperatures (PVT corners). The design methodology presented in this paper minimizes these sensitivities.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90107289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996729
M. Saint-Laurent, V. Oklobdzija, Simon S. Singh, M. Swaminathan
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little energy is just as bad as providing too much. It is also argued that directly trying to minimize the energy-delay product of the sequencing subsystem is practically not the right thing to do. A model for the relationship between supply voltage, clock frequency, and power dissipation is developed and empirically verified for a SPARC V9 microprocessor. An expression for the optimal energy allocation in a system is derived. Then, based on this optimum, a methodology to design energy-efficient systems is proposed.
{"title":"Optimal sequencing energy allocation for CMOS integrated systems","authors":"M. Saint-Laurent, V. Oklobdzija, Simon S. Singh, M. Swaminathan","doi":"10.1109/ISQED.2002.996729","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996729","url":null,"abstract":"All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little energy is just as bad as providing too much. It is also argued that directly trying to minimize the energy-delay product of the sequencing subsystem is practically not the right thing to do. A model for the relationship between supply voltage, clock frequency, and power dissipation is developed and empirically verified for a SPARC V9 microprocessor. An expression for the optimal energy allocation in a system is derived. Then, based on this optimum, a methodology to design energy-efficient systems is proposed.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83316063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996786
T. Sakurai
In this paper, methods to achieve low-power and high-speed VLSI's are described with the emphasis on cooperation between levels. To suppress the leakage current in a standby mode, Boosted Gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, V/sub DD/-hopping and V/sub TH/-hopping are promising, which are cooperative approaches between circuit and software. The power consumed in an interconnect system is another issue in low-voltage deep-submicron designs. A cooperative approach between VLSI and assembly to the interconnect power problem is also discussed.
本文介绍了实现低功耗和高速VLSI的方法，重点是级间协作。为了抑制待机状态下的漏电流，boost Gate MOS (BGMOS)是一种有效的抑制漏电流的方法，它是基于技术层面和电路层面的协同工作。为了降低有源模式下的功率，V/sub DD/跳频和V/sub TH/跳频是一种很有前途的电路与软件的合作方式。在低电压深亚微米设计中，互连系统的功耗是另一个问题。讨论了超大规模集成电路与集成电路合作解决互连功率问题的方法。
{"title":"Low-power and high-speed V VLSI design with low supply voltage through cooperation between levels","authors":"T. Sakurai","doi":"10.1109/ISQED.2002.996786","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996786","url":null,"abstract":"In this paper, methods to achieve low-power and high-speed VLSI's are described with the emphasis on cooperation between levels. To suppress the leakage current in a standby mode, Boosted Gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, V/sub DD/-hopping and V/sub TH/-hopping are promising, which are cooperative approaches between circuit and software. The power consumed in an interconnect system is another issue in low-voltage deep-submicron designs. A cooperative approach between VLSI and assembly to the interconnect power problem is also discussed.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83429529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996721
Ting-Yuan Wang, C. C. Chen
This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The space-sizing which allows the length to change gives more flexibility in solving practical problems. There are two major contributions of this paper. First, we prove that for general topology, a relaxed version of this problem is also convex. Second, we present the sequential network simplex algorithm which can solve those problems with extreme efficiency. Experimental results on several large scale problems, using a PC with a 500-MHZ Pentium III processor, show that our algorithm can solve problems with hundreds of thousands of variables within a few minutes and has a speed improvement of 25+ over sequential linear programming. Experimental results also show that about 50% of the power delivery area can be reduced using our algorithm.
{"title":"Optimization of the power/ground network wire-sizing and spacing based on sequential network simplex algorithm","authors":"Ting-Yuan Wang, C. C. Chen","doi":"10.1109/ISQED.2002.996721","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996721","url":null,"abstract":"This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The space-sizing which allows the length to change gives more flexibility in solving practical problems. There are two major contributions of this paper. First, we prove that for general topology, a relaxed version of this problem is also convex. Second, we present the sequential network simplex algorithm which can solve those problems with extreme efficiency. Experimental results on several large scale problems, using a PC with a 500-MHZ Pentium III processor, show that our algorithm can solve problems with hundreds of thousands of variables within a few minutes and has a speed improvement of 25+ over sequential linear programming. Experimental results also show that about 50% of the power delivery area can be reduced using our algorithm.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84175917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996712
E. Malavasi, S. Zanella, Min Cao, J. Uschersohn, M. Misheloff, C. Guardiani
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew. The methodology is divided in three phases. The first phase is a topological analysis used to screen non-critical network configurations, which does not require computationally expensive steps such as parasitic extraction and circuit-level simulation. The second phase is a detailed nominal skew computation based on accurate 3D extraction, performed on a small set of configurations identified as critical by the topological analysis. The third phase is a variational analysis of the impact of process variations and design parameters on the clock skew, that might induce timing margin violations. This methodology has been implemented for scan chain analysis and validated on an industrial strength test case.
{"title":"Impact analysis of process variability on clock skew","authors":"E. Malavasi, S. Zanella, Min Cao, J. Uschersohn, M. Misheloff, C. Guardiani","doi":"10.1109/ISQED.2002.996712","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996712","url":null,"abstract":"This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew. The methodology is divided in three phases. The first phase is a topological analysis used to screen non-critical network configurations, which does not require computationally expensive steps such as parasitic extraction and circuit-level simulation. The second phase is a detailed nominal skew computation based on accurate 3D extraction, performed on a small set of configurations identified as critical by the topological analysis. The third phase is a variational analysis of the impact of process variations and design parameters on the clock skew, that might induce timing margin violations. This methodology has been implemented for scan chain analysis and validated on an industrial strength test case.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89714324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996730
J. M. Gilbert, I. Bell, D. R. Johnson
This paper describes the adaptation of the conformability analysis technique to the assessment of functional, manufacturing and test capability of PCB level electronic circuits. It combines process capability indices and failure modes and effects analysis (FMEA) with cost mapping to allow the quality costs associated with design and manufacture induced faults to be estimated and the effectiveness of test strategies in reducing these costs to be determined. It allows the trade-off between these costs and the component, manufacturing process and test costs to be explored. The technique is particularly applicable to the relatively low complexity analogue and mixed signal safety critical circuits typically found in automotive and aircraft electronic systems.
{"title":"Design, manufacture and test-quality cost estimation","authors":"J. M. Gilbert, I. Bell, D. R. Johnson","doi":"10.1109/ISQED.2002.996730","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996730","url":null,"abstract":"This paper describes the adaptation of the conformability analysis technique to the assessment of functional, manufacturing and test capability of PCB level electronic circuits. It combines process capability indices and failure modes and effects analysis (FMEA) with cost mapping to allow the quality costs associated with design and manufacture induced faults to be estimated and the effectiveness of test strategies in reducing these costs to be determined. It allows the trade-off between these costs and the component, manufacturing process and test costs to be explored. The technique is particularly applicable to the relatively low complexity analogue and mixed signal safety critical circuits typically found in automotive and aircraft electronic systems.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87595647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996700
A. Slusarczyk, L. Józwiak
One of the main problems in design of modem microelectronic systems is achieving consistent high quality results along the entire EDA tool chain. Using the sequential logic synthesis tools for a case study, this paper shows how important is the consistent tool collaboration for the quality of the final result. In the paper, a new uniform and consistent information-driven logic synthesis approach is proposed and compared to some other logic synthesis flows, including the traditional flow involving JEDI and SIS. The experimental research demonstrates that the quality of the new information-driven logic synthesis tools and the harmony of the new uniform approach results in much better circuits than the circuits from all other flows. The information-based synthesis flow produced circuits that are on average 25% smaller and 30% faster than the circuits from traditional flow.
{"title":"Interoperability and quality of new EDA tools for sequential logic synthesis","authors":"A. Slusarczyk, L. Józwiak","doi":"10.1109/ISQED.2002.996700","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996700","url":null,"abstract":"One of the main problems in design of modem microelectronic systems is achieving consistent high quality results along the entire EDA tool chain. Using the sequential logic synthesis tools for a case study, this paper shows how important is the consistent tool collaboration for the quality of the final result. In the paper, a new uniform and consistent information-driven logic synthesis approach is proposed and compared to some other logic synthesis flows, including the traditional flow involving JEDI and SIS. The experimental research demonstrates that the quality of the new information-driven logic synthesis tools and the harmony of the new uniform approach results in much better circuits than the circuits from all other flows. The information-based synthesis flow produced circuits that are on average 25% smaller and 30% faster than the circuits from traditional flow.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89653374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996750
G. Jervan, Zebo Peng, R. Ubar, H. Kruus
This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the rest process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.
{"title":"A hybrid BIST architecture and its optimization for SoC testing","authors":"G. Jervan, Zebo Peng, R. Ubar, H. Kruus","doi":"10.1109/ISQED.2002.996750","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996750","url":null,"abstract":"This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the rest process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82387468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-03-18DOI: 10.1109/ISQED.2002.996793
M. Leong, H. Wong, E. Nowak, J. Kedzierski, E. E. Jones
The double-gate FET is widely recognized as the prime candidate for the ultimate scaling of FETs to the shortest channel length. From the device integration point of view, the attainment of low extrinsic resistance, carrier transport in the double-gated thin silicon channel and threshold voltage control, remained significant obstacles to high-performance double-gate CMOS structures. We report how these issues were addressed to achieve world-record double-gate device performance. The second gate in a double-gate device can be utilized for low-power and mixed-signal applications. The flexibility of individually controlling the two gates provides opportunities for overall system performance improvement. Ultra-low voltage operation of double-gate CMOS inverters was demonstrated. Finally, we discuss the migration of existing circuit/layout designs to double-gate device technology.
{"title":"High performance double-gate device technology challenges and opportunities","authors":"M. Leong, H. Wong, E. Nowak, J. Kedzierski, E. E. Jones","doi":"10.1109/ISQED.2002.996793","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996793","url":null,"abstract":"The double-gate FET is widely recognized as the prime candidate for the ultimate scaling of FETs to the shortest channel length. From the device integration point of view, the attainment of low extrinsic resistance, carrier transport in the double-gated thin silicon channel and threshold voltage control, remained significant obstacles to high-performance double-gate CMOS structures. We report how these issues were addressed to achieve world-record double-gate device performance. The second gate in a double-gate device can be utilized for low-power and mixed-signal applications. The flexibility of individually controlling the two gates provides opportunities for overall system performance improvement. Ultra-low voltage operation of double-gate CMOS inverters was demonstrated. Finally, we discuss the migration of existing circuit/layout designs to double-gate device technology.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76530859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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