Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996773
A. Maheshwari, W. Burleson, R. Tessier
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consumption due to limited battery life. This paper explores architecture, logic and circuit level approaches to this tradeoff. Fault tolerance techniques at the architecture level can be broadly classified into spatial or temporal redundancy. Using an example of counters (binary and Gray) we show that temporal redundancy is best suited for these ultra-low power and low performance systems as it consumes 30% less power than an area redundant technique. Circuit techniques allow power-reliability tradeoffs of about 50% in each measure. A methodology is developed based on low-level fault simulation using SPICE, which allows detailed circuit models for both power consumption and reliability in current and future CMOS technology.
{"title":"Trading off reliability and power-consumption in ultra-low power systems","authors":"A. Maheshwari, W. Burleson, R. Tessier","doi":"10.1109/ISQED.2002.996773","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996773","url":null,"abstract":"Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consumption due to limited battery life. This paper explores architecture, logic and circuit level approaches to this tradeoff. Fault tolerance techniques at the architecture level can be broadly classified into spatial or temporal redundancy. Using an example of counters (binary and Gray) we show that temporal redundancy is best suited for these ultra-low power and low performance systems as it consumes 30% less power than an area redundant technique. Circuit techniques allow power-reliability tradeoffs of about 50% in each measure. A methodology is developed based on low-level fault simulation using SPICE, which allows detailed circuit models for both power consumption and reliability in current and future CMOS technology.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73025762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996687
R. Reif, A. Fan, Kuan-Neng Chen, Shamik Das
The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.
{"title":"Fabrication technologies for three-dimensional integrated circuits","authors":"R. Reif, A. Fan, Kuan-Neng Chen, Shamik Das","doi":"10.1109/ISQED.2002.996687","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996687","url":null,"abstract":"The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73187479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996783
V. Zolotov, D. Blaauw, R. Panda, C. Oh
Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linearly to simplify the analysis and increase its efficiency. In this paper, we show that this linear assumption results in a significant underestimation of the noise, due to the nonlinear behavior of the driver gate, and hence can lead to many undetected noise failures in the design. Since complete nonlinear simulation is too slow for large cell-based designs, we propose a new linear model that accurately captures the nonlinear behavior of the driver gate. We propose three iterative methods for computing the model parameters of this linear model. Results are presented to demonstrate the accuracy of the proposed approach on several industrial designs.
{"title":"Noise injection and propagation in high performance designs","authors":"V. Zolotov, D. Blaauw, R. Panda, C. Oh","doi":"10.1109/ISQED.2002.996783","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996783","url":null,"abstract":"Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linearly to simplify the analysis and increase its efficiency. In this paper, we show that this linear assumption results in a significant underestimation of the noise, due to the nonlinear behavior of the driver gate, and hence can lead to many undetected noise failures in the design. Since complete nonlinear simulation is too slow for large cell-based designs, we propose a new linear model that accurately captures the nonlinear behavior of the driver gate. We propose three iterative methods for computing the model parameters of this linear model. Results are presented to demonstrate the accuracy of the proposed approach on several industrial designs.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74041497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996709
D. Venuto, M. Ohletz, B. Riccò
The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.
{"title":"Testing of analogue circuits via (standard) digital gates","authors":"D. Venuto, M. Ohletz, B. Riccò","doi":"10.1109/ISQED.2002.996709","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996709","url":null,"abstract":"The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74767258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996782
E. Acar, S. Nassif, Y. Liu, L. Pileggi
Interconnect parameter variations are more significant in the nanometer regime due to the increase in relative tolerances for upcoming integration technologies. As several variability studies indicate the significant role of the interconnect on system performance, the analysis of linear models is extremely crucial. Contrary to devices, the extreme case scenarios do not apply for context-dependent interconnect, necessitating a statistical analysis framework. A previously proposed approach to represent interconnect models in terms of global interconnect parameters is necessary in such frameworks. In this paper we present efficient ways of simulating these variational interconnect models in the presence of nonlinear devices. We demonstrate our methodology by incorporating variational interconnect models into transistor-level simulation with accurate nonlinear device models.
{"title":"Time-domain simulation of variational interconnect models","authors":"E. Acar, S. Nassif, Y. Liu, L. Pileggi","doi":"10.1109/ISQED.2002.996782","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996782","url":null,"abstract":"Interconnect parameter variations are more significant in the nanometer regime due to the increase in relative tolerances for upcoming integration technologies. As several variability studies indicate the significant role of the interconnect on system performance, the analysis of linear models is extremely crucial. Contrary to devices, the extreme case scenarios do not apply for context-dependent interconnect, necessitating a statistical analysis framework. A previously proposed approach to represent interconnect models in terms of global interconnect parameters is necessary in such frameworks. In this paper we present efficient ways of simulating these variational interconnect models in the presence of nonlinear devices. We demonstrate our methodology by incorporating variational interconnect models into transistor-level simulation with accurate nonlinear device models.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81686169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996771
D. Scott, Shaoping Tang, Song Zhao, M. Nandakumar
The limitations of implementing low leakage schemes and their application to current state of the art components is discussed In addition to source subthreshold leakage, both gate induced diode leakage current and tunneling gate leakage current must be comprehended A viable leakage reduction strategy requires extensive modeling of circuits in the standby mode as well as new demands on the understanding of transistor physics. The ramifications of the physics of the behavior of transistors under conditions of high electric fields apply not only at the circuit level but can also impact the chip level system. In the coming applications of mobile electronics, understanding of this concept is critical.
{"title":"Device physics impact on low leakage, high speed DSP design techniques","authors":"D. Scott, Shaoping Tang, Song Zhao, M. Nandakumar","doi":"10.1109/ISQED.2002.996771","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996771","url":null,"abstract":"The limitations of implementing low leakage schemes and their application to current state of the art components is discussed In addition to source subthreshold leakage, both gate induced diode leakage current and tunneling gate leakage current must be comprehended A viable leakage reduction strategy requires extensive modeling of circuits in the standby mode as well as new demands on the understanding of transistor physics. The ramifications of the physics of the behavior of transistors under conditions of high electric fields apply not only at the circuit level but can also impact the chip level system. In the coming applications of mobile electronics, understanding of this concept is critical.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85685273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996762
Sumit Ghosh
This paper has traced the VHDL architects' journey into the world of delta delay including the original need for zero delay usage that evolved from a misconception that zero delays enhance simulation throughput without any penalty, the subsequent difficulties with the VHDL implementation of zero delay, the adapting of Conlan's BCL model of time into VHDL as delta delay without a clear understanding of the consequences, and the problems that confront VHDL today. This paper has presented a simple solution to the problem that involves the elimination of zero delay usage and the specification of actual component delay values in terms of universal time.
{"title":"In search of the origin of VHDL's delta delays","authors":"Sumit Ghosh","doi":"10.1109/ISQED.2002.996762","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996762","url":null,"abstract":"This paper has traced the VHDL architects' journey into the world of delta delay including the original need for zero delay usage that evolved from a misconception that zero delays enhance simulation throughput without any penalty, the subsequent difficulties with the VHDL implementation of zero delay, the adapting of Conlan's BCL model of time into VHDL as delta delay without a clear understanding of the consequences, and the problems that confront VHDL today. This paper has presented a simple solution to the problem that involves the elimination of zero delay usage and the specification of actual component delay values in terms of universal time.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88067679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996726
W. Beyene, Xingchao Yuan
An accurate transient analysis of a package interconnect requires the modeling and analysis of conductor and dielectric losses, as well as other high-frequency effects of 3D structures. The skin effect and dispersion of interconnects are more accurately modeled in frequency domain. Consequently, the complete time-domain simulation of such a system is only possible using convolution techniques. Although the convolution method is well understood, the application of windowing for interconnect analysis is less so. In this paper, we present the practical considerations of window selection and its application to improve the accuracy of convolution simulators. We introduce the Tukey window and study the tradeoff between how smoothly a datum can be set to zero to avoid aliasing and suppress ripples and how much information tapering will discount at the edge of the window in order to obtain meaningful results. The bandlimiting effects of the Tukey window and other well-known windows are also compared. Finally, wirebond PBGA package and PCB-connector system are analyzed using the scattering parameters obtained from simulation and measurement, respectively, to verify the validity and accuracy of the method.
{"title":"On the use of windows for accurate analysis of package interconnects","authors":"W. Beyene, Xingchao Yuan","doi":"10.1109/ISQED.2002.996726","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996726","url":null,"abstract":"An accurate transient analysis of a package interconnect requires the modeling and analysis of conductor and dielectric losses, as well as other high-frequency effects of 3D structures. The skin effect and dispersion of interconnects are more accurately modeled in frequency domain. Consequently, the complete time-domain simulation of such a system is only possible using convolution techniques. Although the convolution method is well understood, the application of windowing for interconnect analysis is less so. In this paper, we present the practical considerations of window selection and its application to improve the accuracy of convolution simulators. We introduce the Tukey window and study the tradeoff between how smoothly a datum can be set to zero to avoid aliasing and suppress ripples and how much information tapering will discount at the edge of the window in order to obtain meaningful results. The bandlimiting effects of the Tukey window and other well-known windows are also compared. Finally, wirebond PBGA package and PCB-connector system are analyzed using the scattering parameters obtained from simulation and measurement, respectively, to verify the validity and accuracy of the method.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87722890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996774
P. Beerel
While ultra-deep-submicron design presents increasingly difficult challenges for standard synchronous design practices, recent research in asynchronous design techniques is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low-power, the growing challenge of predicting increasing impact of wire load and delay, and the performance penalty associated with supporting communication between different clock domains. This paper reviews the different solutions to these problems that the spectrum of existing asynchronous design techniques support. It focuses on techniques for fine-grain two-dimensional pipelining that yield ultra-high-speed at nominal power supplies and very low-energy at reduced power supplies.
{"title":"Asynchronous circuits: an increasingly practical design solution","authors":"P. Beerel","doi":"10.1109/ISQED.2002.996774","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996774","url":null,"abstract":"While ultra-deep-submicron design presents increasingly difficult challenges for standard synchronous design practices, recent research in asynchronous design techniques is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low-power, the growing challenge of predicting increasing impact of wire load and delay, and the performance penalty associated with supporting communication between different clock domains. This paper reviews the different solutions to these problems that the spectrum of existing asynchronous design techniques support. It focuses on techniques for fine-grain two-dimensional pipelining that yield ultra-high-speed at nominal power supplies and very low-energy at reduced power supplies.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84329649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996795
C. Wasshuber
How it works: a short and simple introduction to the underlying physics of single electronics is given. Relevant energies, charging, tunneling and Coulomb blockade are explained with simple concepts and analogies. How it is used: an overview of possible applications is given. A focus is placed on the most promising ones such as memories and applications in metrology. The author also mentions open challenges such as random background charge fluctuations and manufacturing methods. How it is simulated: three simulation methods, Monte Carlo, Master Equation and Spice macro-models, are introduced and compared. The author touches on appropriate random number generators, variance reducing methods and make comparison to measurements.
{"title":"Single-electronics - how it works. How it's used. How it's simulated","authors":"C. Wasshuber","doi":"10.1109/ISQED.2002.996795","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996795","url":null,"abstract":"How it works: a short and simple introduction to the underlying physics of single electronics is given. Relevant energies, charging, tunneling and Coulomb blockade are explained with simple concepts and analogies. How it is used: an overview of possible applications is given. A focus is placed on the most promising ones such as memories and applications in metrology. The author also mentions open challenges such as random background charge fluctuations and manufacturing methods. How it is simulated: three simulation methods, Monte Carlo, Master Equation and Spice macro-models, are introduced and compared. The author touches on appropriate random number generators, variance reducing methods and make comparison to measurements.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83371131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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