Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996755
P. Lala, B. K. Kumar
This paper proposes an architecture for implementing self-healing digital systems. The adopted self-healing mechanism is inspired by the human immune system. A digital system based on the proposed architecture is composed of a number of functional cells that are interconnected to perform a desired function. As in the immune system, the error detection in the cell based digital system is done without using any centralized fault detection mechanism. Once a faulty cell is identified a spare cell replaces it; the spare cells are distributed throughout the system.
{"title":"Human immune system inspired architecture for self-healing digital systems","authors":"P. Lala, B. K. Kumar","doi":"10.1109/ISQED.2002.996755","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996755","url":null,"abstract":"This paper proposes an architecture for implementing self-healing digital systems. The adopted self-healing mechanism is inspired by the human immune system. A digital system based on the proposed architecture is composed of a number of functional cells that are interconnected to perform a desired function. As in the immune system, the error detection in the cell based digital system is done without using any centralized fault detection mechanism. Once a faulty cell is identified a spare cell replaces it; the spare cells are distributed throughout the system.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82797189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996689
K. Banerjee, A. Mehrotra
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS (1999), interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.
{"title":"Inductance aware interconnect scaling","authors":"K. Banerjee, A. Mehrotra","doi":"10.1109/ISQED.2002.996689","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996689","url":null,"abstract":"This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS (1999), interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82451100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996799
W. Dai, M. Courtoy
A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'hub' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.
{"title":"Hierarchical front-end physical design solution drives modified hand-off","authors":"W. Dai, M. Courtoy","doi":"10.1109/ISQED.2002.996799","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996799","url":null,"abstract":"A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'hub' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80545490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996723
G. Bai, I. Hajj
This paper presents a frequency-domain technique for finding the worst-case time-domain voltage variations in the RLC power bus of digital VLSI circuits. Pattern independent maximum envelope currents are used for the logic gates and macroblocks. The voltage drop/surge at a power bus node is expressed in term of the currents using sensitivity analysis. The sensitivity information together with an optimization procedure are applied to find the upper-bounds on the voltage variations at the targeted bus nodes. The resonance problem due to the on-chip RLC power distribution network is analyzed base on the frequency-domain sensitivity analysis. Comparisons to SPICE simulation of circuits extracted from layouts are used to validate our approach.
{"title":"Simultaneous switching noise and resonance analysis of on-chip power distribution network","authors":"G. Bai, I. Hajj","doi":"10.1109/ISQED.2002.996723","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996723","url":null,"abstract":"This paper presents a frequency-domain technique for finding the worst-case time-domain voltage variations in the RLC power bus of digital VLSI circuits. Pattern independent maximum envelope currents are used for the logic gates and macroblocks. The voltage drop/surge at a power bus node is expressed in term of the currents using sensitivity analysis. The sensitivity information together with an optimization procedure are applied to find the upper-bounds on the voltage variations at the targeted bus nodes. The resonance problem due to the on-chip RLC power distribution network is analyzed base on the frequency-domain sensitivity analysis. Comparisons to SPICE simulation of circuits extracted from layouts are used to validate our approach.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82166742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996747
E. Kalligeros, X. Kavousianos, D. Bakalis, D. Nikolos
Built-in self-test (BIST) is an effective approach for testing large and complex circuits. When BIST is used, a test pattern generator (TPG), a test response verifier and a BIST controller accompany the circuit under test (CUT) in the chip, creating a self-testable circuit. In this paper we propose a new algorithm for seeds selection in LFSR (linear feedback shift register) based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.
{"title":"An efficient seeds selection method for LFSR-based test-per-clock BIST","authors":"E. Kalligeros, X. Kavousianos, D. Bakalis, D. Nikolos","doi":"10.1109/ISQED.2002.996747","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996747","url":null,"abstract":"Built-in self-test (BIST) is an effective approach for testing large and complex circuits. When BIST is used, a test pattern generator (TPG), a test response verifier and a BIST controller accompany the circuit under test (CUT) in the chip, creating a self-testable circuit. In this paper we propose a new algorithm for seeds selection in LFSR (linear feedback shift register) based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89577658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996717
Chul-Hong Park, S. Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong
The hybrid PPC (process proximity correction) has been one of the inevitable methods for the sub-wavelength lithography to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the flow of hybrid PPC classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a model accuracy, and the extension of the contact overlap margin. Furthermore, the effective method of an empirical model is exploited to compensate the nonlinear etch proximity effect. The statistical method based on the real pattern geometry is also constructed to reflect the process issues in real manufacturing. From this work with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared with the rule-based PPC has been achieved.
{"title":"A hybrid PPC method based on the empirical etch model for the 0.14/spl mu/m DRAM generation and beyond","authors":"Chul-Hong Park, S. Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong","doi":"10.1109/ISQED.2002.996717","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996717","url":null,"abstract":"The hybrid PPC (process proximity correction) has been one of the inevitable methods for the sub-wavelength lithography to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the flow of hybrid PPC classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a model accuracy, and the extension of the contact overlap margin. Furthermore, the effective method of an empirical model is exploited to compensate the nonlinear etch proximity effect. The statistical method based on the real pattern geometry is also constructed to reflect the process issues in real manufacturing. From this work with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared with the rule-based PPC has been achieved.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79273683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996781
M. Becer, R. Panda, D. Blaauw, I. Hajj
One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the post-route design stage when detailed parasitic information is available. However, noise problems identified at this stage of design cycle are very difficult to fix due to the limited flexibility in the design and may, cause additional iterations of routing and placement, adding costly delays to time-to-market. In this paper we introduce an estimated, congestion-based pre-route noise analysis approach to identify post-route noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design is not yet available at this point, we propose a novel probabilistic method for capacitance extraction. We present results on two high performance microprocessors in 0.18 /spl mu/ technology that demonstrate the effectiveness of the proposed approach.
{"title":"Pre-route noise estimation in deep submicron integrated circuits","authors":"M. Becer, R. Panda, D. Blaauw, I. Hajj","doi":"10.1109/ISQED.2002.996781","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996781","url":null,"abstract":"One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the post-route design stage when detailed parasitic information is available. However, noise problems identified at this stage of design cycle are very difficult to fix due to the limited flexibility in the design and may, cause additional iterations of routing and placement, adding costly delays to time-to-market. In this paper we introduce an estimated, congestion-based pre-route noise analysis approach to identify post-route noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design is not yet available at this point, we propose a novel probabilistic method for capacitance extraction. We present results on two high performance microprocessors in 0.18 /spl mu/ technology that demonstrate the effectiveness of the proposed approach.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78056371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996735
Ulf Schlichtmann
Summary form only given. Embedded memories increasingly dominate SoC designs - whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the 50 nm node by the end of the decade. Therefore, even more than at present, the success of future SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges are outlined and solutions are proposed. The focus of the discussion is on SRAM/ROM, but other technologies such as eDRAM and "1T SRAM" are also addressed.
{"title":"Tomorrows high-quality SoCs require high-quality embedded memories today","authors":"Ulf Schlichtmann","doi":"10.1109/ISQED.2002.996735","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996735","url":null,"abstract":"Summary form only given. Embedded memories increasingly dominate SoC designs - whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the 50 nm node by the end of the decade. Therefore, even more than at present, the success of future SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges are outlined and solutions are proposed. The focus of the discussion is on SRAM/ROM, but other technologies such as eDRAM and \"1T SRAM\" are also addressed.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74096122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996697
Terry Blanchard, Rick Ferreri, J. Wilmore
The rapidly increasing complexity of integrated circuit design can only be addressed effectively by a design system architecture that supports very efficient, high-quality sharing of IC design data. Integration of the wide variety of tools required to design and verify the performance and quality of ICs can no longer depend on low-bandwidth file formats. Rather, an application programming interface (API) to a standard information model (IM) that provides access to a shared database is an essential infrastructure component of today's IC design systems. Furthermore, this design data API should be standard across the IC CAD industry so that design systems can efficiently draw from best-of-class applications from all sources in the EDA industry. The tight coupling of all tools through a common IM/API enables rapid design convergence with an earlier emphasis on quality issues, which results in higher quality ICs while meeting aggressive time-to-market demands.
{"title":"The OpenAccess coalition - the drive to an open industry standard information model, API, and reference implementation for IC design data","authors":"Terry Blanchard, Rick Ferreri, J. Wilmore","doi":"10.1109/ISQED.2002.996697","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996697","url":null,"abstract":"The rapidly increasing complexity of integrated circuit design can only be addressed effectively by a design system architecture that supports very efficient, high-quality sharing of IC design data. Integration of the wide variety of tools required to design and verify the performance and quality of ICs can no longer depend on low-bandwidth file formats. Rather, an application programming interface (API) to a standard information model (IM) that provides access to a shared database is an essential infrastructure component of today's IC design systems. Furthermore, this design data API should be standard across the IC CAD industry so that design systems can efficiently draw from best-of-class applications from all sources in the EDA industry. The tight coupling of all tools through a common IM/API enables rapid design convergence with an earlier emphasis on quality issues, which results in higher quality ICs while meeting aggressive time-to-market demands.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74430397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996790
Y. Aghaghiri, F. Fallah, Massoud Pedram
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the limited-weight codes and, with enhancements to make it adaptive and irredundant, results in up to 89% reduction in the instruction bus switching activity, at the expense of a small area overhead.
{"title":"ALBORZ: Address Level Bus Power Optimization","authors":"Y. Aghaghiri, F. Fallah, Massoud Pedram","doi":"10.1109/ISQED.2002.996790","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996790","url":null,"abstract":"In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the limited-weight codes and, with enhancements to make it adaptive and irredundant, results in up to 89% reduction in the instruction bus switching activity, at the expense of a small area overhead.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87423710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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