Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996761
A. Hajjar, Tom Chen
In order to improve the effectiveness of simulation-based behavioral verification, it is important to determine when to stop the current test strategy and to switch to an expectantly more rewarding test strategy. The location of a stopping point is dependent on the statistical model one chooses to describe the coverage behavior during verification. In this paper, we present dynamic Bayesian (DB) and confidence-based dynamic Bayesian (CDB) stopping rules for behavioral VHDL model verification. The statistical assumptions of the proposed stopping rules are based on experimental evaluation of probability distribution functions and correlation functions. Fourteen behavioral VHDL models were experimented with to determine the high efficiency of the proposed stopping rules over the existing ones. Results show that the DB and the CDB stopping rules outperform all the existing stopping rules with an average improvement of at least 69% in coverage per testing patterns used.
{"title":"Improving the efficiency and quality of simulation-based behavioral model verification using dynamic Bayesian criteria","authors":"A. Hajjar, Tom Chen","doi":"10.1109/ISQED.2002.996761","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996761","url":null,"abstract":"In order to improve the effectiveness of simulation-based behavioral verification, it is important to determine when to stop the current test strategy and to switch to an expectantly more rewarding test strategy. The location of a stopping point is dependent on the statistical model one chooses to describe the coverage behavior during verification. In this paper, we present dynamic Bayesian (DB) and confidence-based dynamic Bayesian (CDB) stopping rules for behavioral VHDL model verification. The statistical assumptions of the proposed stopping rules are based on experimental evaluation of probability distribution functions and correlation functions. Fourteen behavioral VHDL models were experimented with to determine the high efficiency of the proposed stopping rules over the existing ones. Results show that the DB and the CDB stopping rules outperform all the existing stopping rules with an average improvement of at least 69% in coverage per testing patterns used.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"51 1","pages":"304-309"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87567786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996800
C. C. Chen, Ed Cheng
SoC (system on a chip) design creates tremendous design challenges to the traditional VLSI ASIC design. It covers not only the traditional DSM (deep sub-micron) issues but also the integration issues such as IP and signal integrity especially for integrated digital/analog system such as Bluetooth. Besides. power consumption and power delivery also impose huge design constraints to the already difficult situation especially for the portable and mobile devices. This talk will introduce and analysis the potential SoC issues and potential solutions from the architecture level to the circuit level.
{"title":"Future SoC design challenges and solutions","authors":"C. C. Chen, Ed Cheng","doi":"10.1109/ISQED.2002.996800","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996800","url":null,"abstract":"SoC (system on a chip) design creates tremendous design challenges to the traditional VLSI ASIC design. It covers not only the traditional DSM (deep sub-micron) issues but also the integration issues such as IP and signal integrity especially for integrated digital/analog system such as Bluetooth. Besides. power consumption and power delivery also impose huge design constraints to the already difficult situation especially for the portable and mobile devices. This talk will introduce and analysis the potential SoC issues and potential solutions from the architecture level to the circuit level.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"22 1","pages":"534-537"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996778
S. Reda, R. Drechsler, A. Orailoglu
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.
{"title":"On the relation between SAT and BDDs for equivalence checking","authors":"S. Reda, R. Drechsler, A. Orailoglu","doi":"10.1109/ISQED.2002.996778","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996778","url":null,"abstract":"State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"40 1","pages":"394-399"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76189605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996740
D. Pamunuwa, H. Tenhunen
Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).
{"title":"On dynamic delay and repeater insertion in distributed capacitively coupled interconnects","authors":"D. Pamunuwa, H. Tenhunen","doi":"10.1109/ISQED.2002.996740","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996740","url":null,"abstract":"Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"20 1","pages":"240-245"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88588742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996792
P. Su, S. Fung, Weidong Liu, C. Hu
In this, work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit, designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.
{"title":"Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD","authors":"P. Su, S. Fung, Weidong Liu, C. Hu","doi":"10.1109/ISQED.2002.996792","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996792","url":null,"abstract":"In this, work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit, designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"956 1","pages":"487-491"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85616100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996770
M. Sahinoglu, Scott Glover
This paper argues that software testing can be less thorough yet more cost-efficient if applied in a well-managed, empirical manner across the entire Software Development Life Cycle (SDLC). This is done by showing the cost-benefit analyses among other criteria. To ensure success, testing must be planned and executed within an Earned Value Management (EVM) paradigm as the experiment is conducted on a statistical-process controlled mindset. The Stopping Rule (MESAT) is applied to an actual embedded-chip software development cycle to show potential gains compared to archaic testing methods or none that were used. The result is that a considerable percentage of the particular testing effort could have been saved under usual circumstances, had the testing been planned and executed under EVM with the MESAT algorithm.
{"title":"Economic analysis of a stopping-rule in branch coverage testing","authors":"M. Sahinoglu, Scott Glover","doi":"10.1109/ISQED.2002.996770","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996770","url":null,"abstract":"This paper argues that software testing can be less thorough yet more cost-efficient if applied in a well-managed, empirical manner across the entire Software Development Life Cycle (SDLC). This is done by showing the cost-benefit analyses among other criteria. To ensure success, testing must be planned and executed within an Earned Value Management (EVM) paradigm as the experiment is conducted on a statistical-process controlled mindset. The Stopping Rule (MESAT) is applied to an actual embedded-chip software development cycle to show potential gains compared to archaic testing methods or none that were used. The result is that a considerable percentage of the particular testing effort could have been saved under usual circumstances, had the testing been planned and executed under EVM with the MESAT algorithm.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"47 1","pages":"341-346"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84760268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996787
R. Marculescu, Diana Marculescu
This paper introduces colloidal computing as an alternative to the classical view on computing systems in terms of design feasibility, application adaptability and better energy-performance trade-offs. In colloidal computing, simple per computational particles are dispersed into a communication medium which is inexpensive, (perhaps) unreliable, yet sufficiently fast. This type of clustering into computationally intensive kernels with loose inter-particle communication, but tight intra-particle communication is typical not only for the underlying hardware, but also for the actual application which runs on it. We believe that the colloidal model is appropriate to describe the next generation of embedded systems. For these systems, a significantly better design quality can be obtained via run-time trade-offs and application-driven adaptability, as opposed to classical systems where optimizations are sought in a rather static manner.
{"title":"Does Q = MC/sup 2/? (On the relationship between Quality in electronic design and the Model of Colloidal Computing)","authors":"R. Marculescu, Diana Marculescu","doi":"10.1109/ISQED.2002.996787","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996787","url":null,"abstract":"This paper introduces colloidal computing as an alternative to the classical view on computing systems in terms of design feasibility, application adaptability and better energy-performance trade-offs. In colloidal computing, simple per computational particles are dispersed into a communication medium which is inexpensive, (perhaps) unreliable, yet sufficiently fast. This type of clustering into computationally intensive kernels with loose inter-particle communication, but tight intra-particle communication is typical not only for the underlying hardware, but also for the actual application which runs on it. We believe that the colloidal model is appropriate to describe the next generation of embedded systems. For these systems, a significantly better design quality can be obtained via run-time trade-offs and application-driven adaptability, as opposed to classical systems where optimizations are sought in a rather static manner.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"11 1","pages":"451-457"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88899528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996776
S. Qadeer, S. Tasiran
Ensuring the functional correctness of hardware early in the design cycle is crucial for both economic and methodological reasons. However, current verification techniques are inadequate for industrial designs. Formal verification techniques are exhaustive but do not scale; partial verification techniques based on simulation scale well but are not exhaustive. This paper discusses promising approaches for improving the scalability of formal verification and comprehensiveness of partial verification.
{"title":"Promising directions in hardware design verification","authors":"S. Qadeer, S. Tasiran","doi":"10.1109/ISQED.2002.996776","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996776","url":null,"abstract":"Ensuring the functional correctness of hardware early in the design cycle is crucial for both economic and methodological reasons. However, current verification techniques are inadequate for industrial designs. Formal verification techniques are exhaustive but do not scale; partial verification techniques based on simulation scale well but are not exhaustive. This paper discusses promising approaches for improving the scalability of formal verification and comprehensiveness of partial verification.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"108 1","pages":"381-387"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84980401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996767
T. Oh, Zhiping Yu, R. Dutton
MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.
{"title":"AC analysis of thin gate oxide MOS with quantum mechanical corrections","authors":"T. Oh, Zhiping Yu, R. Dutton","doi":"10.1109/ISQED.2002.996767","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996767","url":null,"abstract":"MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"41 1","pages":"326-330"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79634769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996716
Daegyu Lee, Jincheol Yoo, Kyusun Choi
The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.
本文介绍了flash a /D转换器比较器电路布置图的设计方法和自动生成。基于阈值逆变量化(TIQ)的A/D转换器需要2/sup n/ - 1个比较器，每个比较器都不同于其他比较器。本文提出的TIQ比较器优化设计方法显著提高了A/D转换器在CMOS工艺变化下的线性度。特别是对CMOS工艺变化的DNL依赖几乎可以消除。将该设计方法整合到软件包中，并生成2/sup n/ - 1优化TIQ比较器布局作为软件包的输出。仿真结果表明了设计方法的有效性。此外，原型芯片已经制造出来，初步测试结果证实了DNL的降低。
{"title":"Design method and automation of comparator generation for flash A/D converter","authors":"Daegyu Lee, Jincheol Yoo, Kyusun Choi","doi":"10.1109/ISQED.2002.996716","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996716","url":null,"abstract":"The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":"21 1","pages":"138-142"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78674459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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