Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219766
T. Mourier, V. Jousseaume, F. Fusalba, C. Lecornec, P. Maury, G. Passemard, P. Haumesser, S. Maitrejean, M. Cordeau, R. Pantel, F. Pierre, M. Fayolle, H. Feldis
65 nm and below technologies will require a combination of porous ultra low k dielectric and copper metallization. Feature size may need the use of conformal metallic barrier deposition methods like CVD or ALD. One of the key issues for integration of such materials come from the tendency for precursor to diffuse through the porous structure degrading effective k value. Various pore sealing methodologies were already investigated and reported. In this paper, we describe a process based on the deposition of a thin dielectric liner that allows sealing of surface pores without impacting too much dielectric properties of ULK material. Physico-chemical analysis were carried out and confirmed by electrical measurements.
{"title":"Porous low k pore sealing process study for 65 nm and below technologies","authors":"T. Mourier, V. Jousseaume, F. Fusalba, C. Lecornec, P. Maury, G. Passemard, P. Haumesser, S. Maitrejean, M. Cordeau, R. Pantel, F. Pierre, M. Fayolle, H. Feldis","doi":"10.1109/IITC.2003.1219766","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219766","url":null,"abstract":"65 nm and below technologies will require a combination of porous ultra low k dielectric and copper metallization. Feature size may need the use of conformal metallic barrier deposition methods like CVD or ALD. One of the key issues for integration of such materials come from the tendency for precursor to diffuse through the porous structure degrading effective k value. Various pore sealing methodologies were already investigated and reported. In this paper, we describe a process based on the deposition of a thin dielectric liner that allows sealing of surface pores without impacting too much dielectric properties of ULK material. Physico-chemical analysis were carried out and confirmed by electrical measurements.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126510852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219717
J. Lu, A. Jindal, Y. Kwon, J. McMahon, M. Rasco, R. Augur, T. Cale, R. Gutmann
Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.
{"title":"Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs","authors":"J. Lu, A. Jindal, Y. Kwon, J. McMahon, M. Rasco, R. Augur, T. Cale, R. Gutmann","doi":"10.1109/IITC.2003.1219717","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219717","url":null,"abstract":"Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133191443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219697
A. Kajita, T. Usui, M. Yamada, E. Ogawa, T. Katata, A. Sakata, H. Miyajima, A. Kojima, R. Kanamura, Y. Ohoka, H. Kawashima, K. Tabuchi, K. Nagahata, Y. Kato, T. Hayashi, S. Kadomura, H. Shibata
100 nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65 nm-node Cu metallization with excellent reliability.
{"title":"Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM","authors":"A. Kajita, T. Usui, M. Yamada, E. Ogawa, T. Katata, A. Sakata, H. Miyajima, A. Kojima, R. Kanamura, Y. Ohoka, H. Kawashima, K. Tabuchi, K. Nagahata, Y. Kato, T. Hayashi, S. Kadomura, H. Shibata","doi":"10.1109/IITC.2003.1219697","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219697","url":null,"abstract":"100 nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65 nm-node Cu metallization with excellent reliability.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219762
A. Naeemi, A. Mulé, J. Meindl
The lengths beyond which board-level optical interconnects are capable of transferring a larger number of bits per second in comparison with electrical interconnects are found for different technology generations. At the 130 nm node, the partition length is 29 cm which reduces to 8.3 cm at the 45 nm because of 7 times faster drivers and 40% finer waveguide pitch.
{"title":"Partition length between board-level electrical and optical interconnects","authors":"A. Naeemi, A. Mulé, J. Meindl","doi":"10.1109/IITC.2003.1219762","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219762","url":null,"abstract":"The lengths beyond which board-level optical interconnects are capable of transferring a larger number of bits per second in comparison with electrical interconnects are found for different technology generations. At the 130 nm node, the partition length is 29 cm which reduces to 8.3 cm at the 45 nm because of 7 times faster drivers and 40% finer waveguide pitch.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123571025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219739
B. White, Q. Wang, D. Economou, P. J. Wolf, T. Jacobs, J. Fourcher
Integration of porous low-k materials for interconnect technology present many challenges to the etch, ash and cleaning processes. One challenge is the post etch removal of photo resist on open porous low-k films. Porous low-k films are very susceptible to damage by plasma processing, which can raise the overall k/sub eff/ of the film. Traditionally, a pure oxygen plasma ash is one method used for photo resist removal on CVD dielectrics. This method cannot be applied to exposed low-k films, because chemical and physical damage occurs. Successful photo resist removal on low-k films can be achieved by reducing chemistries or dilute O/sub 2/ processes in RIE etch tools. This work shows how an energetic neutral oxygen beam can be used to strip photo resist, without damaging the exposed low-k material.
{"title":"Neutral oxygen beam stripping of photo resist on porous ultra low-k materials","authors":"B. White, Q. Wang, D. Economou, P. J. Wolf, T. Jacobs, J. Fourcher","doi":"10.1109/IITC.2003.1219739","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219739","url":null,"abstract":"Integration of porous low-k materials for interconnect technology present many challenges to the etch, ash and cleaning processes. One challenge is the post etch removal of photo resist on open porous low-k films. Porous low-k films are very susceptible to damage by plasma processing, which can raise the overall k/sub eff/ of the film. Traditionally, a pure oxygen plasma ash is one method used for photo resist removal on CVD dielectrics. This method cannot be applied to exposed low-k films, because chemical and physical damage occurs. Successful photo resist removal on low-k films can be achieved by reducing chemistries or dilute O/sub 2/ processes in RIE etch tools. This work shows how an energetic neutral oxygen beam can be used to strip photo resist, without damaging the exposed low-k material.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125535743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219710
N. Hata, C. Negoro, S. Takada, X. Xiao, K. Yamada, T. Kikkawa
The need of introducing higher density of nanopores into interlayer dielectrics to realize k<2.0 increases the danger of pore coagulation to form unexpectedly large 'killer' pores, which cause defects in Cu diffusion barrier layer to lead to device failure. On the other hand, unintentional small micropores with less than 0.7 nm in diameter are also problematic in terms of physico-chemical and mechanical stability. In this work, we employ two different low-k films with k=1.8 and show experimental results on the largeand small-ends of pore size distributions to address most important technological issues in ultra-low-k/Cu interconnects.
{"title":"Integrated characterization of porous low-k films for identifying killer pores and micropores","authors":"N. Hata, C. Negoro, S. Takada, X. Xiao, K. Yamada, T. Kikkawa","doi":"10.1109/IITC.2003.1219710","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219710","url":null,"abstract":"The need of introducing higher density of nanopores into interlayer dielectrics to realize k<2.0 increases the danger of pore coagulation to form unexpectedly large 'killer' pores, which cause defects in Cu diffusion barrier layer to lead to device failure. On the other hand, unintentional small micropores with less than 0.7 nm in diameter are also problematic in terms of physico-chemical and mechanical stability. In this work, we employ two different low-k films with k=1.8 and show experimental results on the largeand small-ends of pore size distributions to address most important technological issues in ultra-low-k/Cu interconnects.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121860809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219702
G. Alers, R. Rozbicki, G. Harm, S. Kailasam, G. Ray, M. Daněk
A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean.
{"title":"Barrier-first integration for improved reliability in copper dual damascene interconnects","authors":"G. Alers, R. Rozbicki, G. Harm, S. Kailasam, G. Ray, M. Daněk","doi":"10.1109/IITC.2003.1219702","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219702","url":null,"abstract":"A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219695
H. Sánchez
The aggressive technology migration of the last 10 years is presented. The circuit-level electrical characteristics of interest ( performance, power, area, noise ) that drive the definition of the back-end of line (BEOL) architecture features ( material, width, pitch, space ) are discussed. The paper finishes with a portrayal of the system, circuit, and technology options that may be needed in the 65 nm to 45 nm technology nodes to maintain scalability.
{"title":"Design implications of low-K","authors":"H. Sánchez","doi":"10.1109/IITC.2003.1219695","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219695","url":null,"abstract":"The aggressive technology migration of the last 10 years is presented. The circuit-level electrical characteristics of interest ( performance, power, area, noise ) that drive the definition of the back-end of line (BEOL) architecture features ( material, width, pitch, space ) are discussed. The paper finishes with a portrayal of the system, circuit, and technology options that may be needed in the 65 nm to 45 nm technology nodes to maintain scalability.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117225102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219763
R. Orobtchouk, N. Schnell, T. Benyattou, J. Gregoire, S. Lardenois, M. Heitzmann, J. Fédéli
This paper describes in details design, fabrication and test of a new compact ARROW optical coupler placed at the border of an IC device. This coupler uses vertical directional coupling between a rib ARROW waveguide and a strip silicon submicronic waveguide assisted by a grating. Modelings show that a 75% coupling efficiency can be obtained while measurements were up to 50%.
{"title":"New ARROW optical coupler for optical interconnect","authors":"R. Orobtchouk, N. Schnell, T. Benyattou, J. Gregoire, S. Lardenois, M. Heitzmann, J. Fédéli","doi":"10.1109/IITC.2003.1219763","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219763","url":null,"abstract":"This paper describes in details design, fabrication and test of a new compact ARROW optical coupler placed at the border of an IC device. This coupler uses vertical directional coupling between a rib ARROW waveguide and a strip silicon submicronic waveguide assisted by a grating. Modelings show that a 75% coupling efficiency can be obtained while measurements were up to 50%.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219755
T. C. Huang, C. H. Yao, W. K. Wan, C. C. Hsia, Ming-Shuo Liang
Stress migration (SM) behavior found on various Cu/Low k interconnects is analyzed in this article. The simulation results demonstrate that the minimum stresses always occur on/near via bottom, which makes the dummy via insertion an effect way relieving SM induced circuit failure. A numerical index reflecting the bulk vacancy density evolution is developed from the simulated stress distribution and aimed at predicting the destination of the migrating vacancies driven by the thermally generated stress gradient of the interconnect system. Though still in its burgeoning stage, the simulated SM behavior using the index compared well against those experimentally collected data.
{"title":"Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer Cu/Low k interconnects","authors":"T. C. Huang, C. H. Yao, W. K. Wan, C. C. Hsia, Ming-Shuo Liang","doi":"10.1109/IITC.2003.1219755","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219755","url":null,"abstract":"Stress migration (SM) behavior found on various Cu/Low k interconnects is analyzed in this article. The simulation results demonstrate that the minimum stresses always occur on/near via bottom, which makes the dummy via insertion an effect way relieving SM induced circuit failure. A numerical index reflecting the bulk vacancy density evolution is developed from the simulated stress distribution and aimed at predicting the destination of the migrating vacancies driven by the thermally generated stress gradient of the interconnect system. Though still in its burgeoning stage, the simulated SM behavior using the index compared well against those experimentally collected data.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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