Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219767
A. Danel, C. Millet, V. Perrut, J. Daviot, V. Jousseaume, O. Louveau, D. Louis
Supercritical CO/sub 2/ (SC CO/sub 2/) processing was investigated for porous ultra low-k dielectric (ULK) and copper for successful Back End Of Line (BEOL) integration. The introduction of specific additives into a SC CO/sub 2/ and careful control of the process parameters lends this technique to a wide range of applications: 1. Stripping: Potentially able to replace both dry ash and wet clean steps to give a single fully compatible process for ULK/Cu. The main current limitation is the removal of resins hardened during dielectric etch. 2. Cleaning: SC CO/sub 2/ is a unique candidate for a dry-in/dry-out process able to clean surface and pores of ULK materials. The removal of Cu rich residues was demonstrated with a chelating agent dissolved in SC CO/sub 2/. 3. Curing of ULK: Contamination by water and organics can significantly damaged ULK material and these can be eliminated by processing in SC CO/sub 2/. Furthermore, by introducing a suitable additive, hexamethyldisilazane (HMDS), subsequent uptake of water was prevented.
{"title":"Supercritical CO/sub 2/ for ULK/Cu integration","authors":"A. Danel, C. Millet, V. Perrut, J. Daviot, V. Jousseaume, O. Louveau, D. Louis","doi":"10.1109/IITC.2003.1219767","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219767","url":null,"abstract":"Supercritical CO/sub 2/ (SC CO/sub 2/) processing was investigated for porous ultra low-k dielectric (ULK) and copper for successful Back End Of Line (BEOL) integration. The introduction of specific additives into a SC CO/sub 2/ and careful control of the process parameters lends this technique to a wide range of applications: 1. Stripping: Potentially able to replace both dry ash and wet clean steps to give a single fully compatible process for ULK/Cu. The main current limitation is the removal of resins hardened during dielectric etch. 2. Cleaning: SC CO/sub 2/ is a unique candidate for a dry-in/dry-out process able to clean surface and pores of ULK materials. The removal of Cu rich residues was demonstrated with a chelating agent dissolved in SC CO/sub 2/. 3. Curing of ULK: Contamination by water and organics can significantly damaged ULK material and these can be eliminated by processing in SC CO/sub 2/. Furthermore, by introducing a suitable additive, hexamethyldisilazane (HMDS), subsequent uptake of water was prevented.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127205903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219744
C. Litteken, R. Dauskardt, T. Scherban, G. Xu, J. Leu, D. Gracias, B. Sun
The interfacial adhesion of lithographically patterned thin film structures has been measured. Fracture mechanics techniques, modified for thin-film geometries, were employed to quantify the interfacial adhesion of patterned arrays containing low-k and Cu metal lines with varying channel length scales, aspect ratios and orientations. The results indicate that interfacial adhesion may be affected by the line structures and their orientation. In addition, the fracture resistance of debonded interface was dependent on the specific low-k material employed in the structure.
{"title":"Interfacial adhesion of thin-film patterned interconnect structures","authors":"C. Litteken, R. Dauskardt, T. Scherban, G. Xu, J. Leu, D. Gracias, B. Sun","doi":"10.1109/IITC.2003.1219744","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219744","url":null,"abstract":"The interfacial adhesion of lithographically patterned thin film structures has been measured. Fracture mechanics techniques, modified for thin-film geometries, were employed to quantify the interfacial adhesion of patterned arrays containing low-k and Cu metal lines with varying channel length scales, aspect ratios and orientations. The results indicate that interfacial adhesion may be affected by the line structures and their orientation. In addition, the fracture resistance of debonded interface was dependent on the specific low-k material employed in the structure.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"123 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128112428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219704
M. Hussein, R. Brain, R. Turkot, J. Leu, V. Singh, S. Sivakumar
We unveil an innovative and manufacturable process technique to pattern dual damascene structures in polymer interlayer dielectric (ILD) without the need for either a permanent hardmask or an embedded etch stop (ES) layer. We introduce a sacrificial hardmask (SAM) and a sacrificial via fill (SAVIL) material to enable the patterning process. Since the hardmask is sacrificial, it is removed at the end of the patterning process without compromising the overall dielectric value of the ILD. The utilization of the SAVIL material provided the trench lithography step with a hole-free, and planar substrate. We demonstrate patterning of dual damascene structures using SAM/SAVIL in a via-first integration scheme through a comparative patterning performance between the SAM/SAVIL-assisted dual damascene patterning and the dual hardmask approach used most in the industry.
{"title":"Dual damascene patterning of polymer interlayer dielectrics","authors":"M. Hussein, R. Brain, R. Turkot, J. Leu, V. Singh, S. Sivakumar","doi":"10.1109/IITC.2003.1219704","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219704","url":null,"abstract":"We unveil an innovative and manufacturable process technique to pattern dual damascene structures in polymer interlayer dielectric (ILD) without the need for either a permanent hardmask or an embedded etch stop (ES) layer. We introduce a sacrificial hardmask (SAM) and a sacrificial via fill (SAVIL) material to enable the patterning process. Since the hardmask is sacrificial, it is removed at the end of the patterning process without compromising the overall dielectric value of the ILD. The utilization of the SAVIL material provided the trench lithography step with a hole-free, and planar substrate. We demonstrate patterning of dual damascene structures using SAM/SAVIL in a via-first integration scheme through a comparative patterning performance between the SAM/SAVIL-assisted dual damascene patterning and the dual hardmask approach used most in the industry.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123454375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219773
Jun Li, Q. Ye, A. Cassell, J. Koehne, H. Ng, Jie Han, M. Meyyappan
The susceptibility of common interconnect metals to electromigration at current densities of 10/sup 6/ A/cm/sup 2/ or greater has been a concern. The ITRS Roadmap emphasizes interconnect technology as a critical element and calls for innovative material and process solutions. This talk will present the potential of carbon nanotubes (CNTs) as interconnects and a processing scheme to integrate them in device fabrication.
{"title":"Carbon nanotube interconnects: a process solution","authors":"Jun Li, Q. Ye, A. Cassell, J. Koehne, H. Ng, Jie Han, M. Meyyappan","doi":"10.1109/IITC.2003.1219773","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219773","url":null,"abstract":"The susceptibility of common interconnect metals to electromigration at current densities of 10/sup 6/ A/cm/sup 2/ or greater has been a concern. The ITRS Roadmap emphasizes interconnect technology as a critical element and calls for innovative material and process solutions. This talk will present the potential of carbon nanotubes (CNTs) as interconnects and a processing scheme to integrate them in device fabrication.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123567389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219727
K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, J. Brewer
The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single chip radio, on-chip and inter-chip communication systems, RFID tags, and others.
{"title":"Wireless communications using integrated antennas","authors":"K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, J. Brewer","doi":"10.1109/IITC.2003.1219727","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219727","url":null,"abstract":"The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single chip radio, on-chip and inter-chip communication systems, RFID tags, and others.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219754
C. Chiang, I-Hsiu Ko, Mao-chieh Chen, Zhen-Cheng Wu, Yung-Cheng Lu, S. Jang, M. Liang
This work investigates the leakage and breakdown mechanisms in the Cu damascene structure with a carbon-doped low-k PECVD organosilicate glass (OSG, k=3) as the intermetal dielectric (IMD) and an /spl alpha/-SiCN(k=5)//spl alpha/-SiC(k=4) bilayer-structured dielectric film as the Cu-cap barrier. It is found that the leakage mechanism between Cu lines is dependent on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier in the Cu damascene structure. In the Cu damascene using an /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier of 40 nm/10 nm or 30 nm/20 nm bilayer thickness, the large leakage current (Frenkel-Poole emission) between Cu lines is attributed to the plenty of interfacial defects, such as cracks, voids, traps or dangling bonds at the /spl alpha/-SiC/OSG interface, which are generated by the larger tensile force of the thicker /spl alpha/-SiC film. On the other hand, the breakdown field and TDDB (time-dependent-dielectric-breakdown) lifetime of the Cu damascene reveal little dependence on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier, and the observed breakdown of the Cu damascene structure is presumably due to dielectric breakdown of the bulk OSG layer.
{"title":"Leakage and breakdown mechanisms in Cu damascene with a bilayer-structured /spl alpha/-SiCN//spl alpha/-SiC dielectric barrier","authors":"C. Chiang, I-Hsiu Ko, Mao-chieh Chen, Zhen-Cheng Wu, Yung-Cheng Lu, S. Jang, M. Liang","doi":"10.1109/IITC.2003.1219754","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219754","url":null,"abstract":"This work investigates the leakage and breakdown mechanisms in the Cu damascene structure with a carbon-doped low-k PECVD organosilicate glass (OSG, k=3) as the intermetal dielectric (IMD) and an /spl alpha/-SiCN(k=5)//spl alpha/-SiC(k=4) bilayer-structured dielectric film as the Cu-cap barrier. It is found that the leakage mechanism between Cu lines is dependent on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier in the Cu damascene structure. In the Cu damascene using an /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier of 40 nm/10 nm or 30 nm/20 nm bilayer thickness, the large leakage current (Frenkel-Poole emission) between Cu lines is attributed to the plenty of interfacial defects, such as cracks, voids, traps or dangling bonds at the /spl alpha/-SiC/OSG interface, which are generated by the larger tensile force of the thicker /spl alpha/-SiC film. On the other hand, the breakdown field and TDDB (time-dependent-dielectric-breakdown) lifetime of the Cu damascene reveal little dependence on the thickness ratio of the /spl alpha/-SiCN//spl alpha/-SiC bilayer barrier, and the observed breakdown of the Cu damascene structure is presumably due to dielectric breakdown of the bulk OSG layer.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219706
E. Cassan, S. Lardenois, D. Pascal, L. Vivien, M. Heitzmann, N. Bouzaida, L. Mollard, R. Orobtchouk, S. Laval
We report in this paper experimental and theoretical results showing that sub-micrometric rib (partially-etched) waveguides on silicon-on insulator (SOI) substrates can be used to achieve a low-loss and compact light distribution for on-chip interconnects in spite of the relatively low light confinement of this kind or waveguides. If compared with on-chip light distribution using SOI strip waveguides (fully-etched), this solution presents advantages such as minimal losses and minimal crosstalk between overlapping perpendicular waveguides.
{"title":"Intra-chip optical interconnects with compact and low-loss light distribution in silicon-on-insulator rib waveguides","authors":"E. Cassan, S. Lardenois, D. Pascal, L. Vivien, M. Heitzmann, N. Bouzaida, L. Mollard, R. Orobtchouk, S. Laval","doi":"10.1109/IITC.2003.1219706","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219706","url":null,"abstract":"We report in this paper experimental and theoretical results showing that sub-micrometric rib (partially-etched) waveguides on silicon-on insulator (SOI) substrates can be used to achieve a low-loss and compact light distribution for on-chip interconnects in spite of the relatively low light confinement of this kind or waveguides. If compared with on-chip light distribution using SOI strip waveguides (fully-etched), this solution presents advantages such as minimal losses and minimal crosstalk between overlapping perpendicular waveguides.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131811694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219696
K. Goto, H. Yuasa, A. Andatsu, M. Matsuura
This paper describes film characterization of Cu diffusion barrier SiC, SiCN and SiCO in detail. Although SiCN and SiCO achieve reduced leakage current and k-value, the biggest challenge is to achieve robust stability in film stress and k value because undesirable N and O doping cause increased film stress and k value after deposition. Fine-tuned SiC makes it possible to greatly reduce leakage current and k value to 3.9. From Bias Temperature Stress (BTS) measurement, our desired SiCN, SiCO and fine-tuned SiC are assured in 10-year durability to electrical Cu diffusion.
{"title":"Film Characterization of Cu diffusion barrier dielectrics for 90 nm and 65 nm technology node Cu interconnects","authors":"K. Goto, H. Yuasa, A. Andatsu, M. Matsuura","doi":"10.1109/IITC.2003.1219696","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219696","url":null,"abstract":"This paper describes film characterization of Cu diffusion barrier SiC, SiCN and SiCO in detail. Although SiCN and SiCO achieve reduced leakage current and k-value, the biggest challenge is to achieve robust stability in film stress and k value because undesirable N and O doping cause increased film stress and k value after deposition. Fine-tuned SiC makes it possible to greatly reduce leakage current and k value to 3.9. From Bias Temperature Stress (BTS) measurement, our desired SiCN, SiCO and fine-tuned SiC are assured in 10-year durability to electrical Cu diffusion.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133674107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219756
M. Kawano, T. Fukase, Y. Yamamoto, T. Ito, S. Yokogawa, H. Tsuda, Y. Kunimune, T. Saitoh, K. Ueno, M. Sekine
Stress-induced voiding (SIV) was investigated for 130 nm node dual-damascene Cu interconnects. Three SIV failure modes were revealed by TEM analyses. Cumulative failure was investigated at various metal widths, via shape and via position on a metal line at 150/spl deg/C at which the maximum failure rate was observed. Stress-induced failure at narrow Cu line was also observed, which is associated with tensile stress in Cu calculated by 3D finite element method (FEM) stress analysis. Stress relaxation by dielectric structure and quenching process were demonstrated based on stress simulation, thus the resulting SIV failure was suppressed.
{"title":"Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding","authors":"M. Kawano, T. Fukase, Y. Yamamoto, T. Ito, S. Yokogawa, H. Tsuda, Y. Kunimune, T. Saitoh, K. Ueno, M. Sekine","doi":"10.1109/IITC.2003.1219756","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219756","url":null,"abstract":"Stress-induced voiding (SIV) was investigated for 130 nm node dual-damascene Cu interconnects. Three SIV failure modes were revealed by TEM analyses. Cumulative failure was investigated at various metal widths, via shape and via position on a metal line at 150/spl deg/C at which the maximum failure rate was observed. Stress-induced failure at narrow Cu line was also observed, which is associated with tensile stress in Cu calculated by 3D finite element method (FEM) stress analysis. Stress relaxation by dielectric structure and quenching process were demonstrated based on stress simulation, thus the resulting SIV failure was suppressed.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124732019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219732
K. Choi, B. Kim, Sang woo Lee, Jong Myeong Lee
ALD-TaN thin films derived from tert-buthyIimidotrisdiethyl-amidotantalum (TBTDET) and tert-amylimidotrisdim-ethylamidotantalum (TAIMATA) precursors for the diffusion barrier in Cu interconnects were developed. The deposition rate of the ALD-TaN process was saturated at 0.4 /spl Aring/ /cycle in a temperature range between 200/spl deg/C and 250/spl deg/C with TBTDET and at 0.2 /spl Aring//cycle in a temperature range between 150/spl deg/C and 200/spl deg/C with TAIMATA. Both precursors provided roughly comparable film properties such as not only excellent conformality but also composition and structure characterized by XPS and XRD, respectively. ALD-TaN films obtained from above precursors yield low via resistance in aluminum interconnects. However, relatively high via resistance was resulted upon Cu integration as compared to PVD-TaN and Al metallization. The superior diffusion barrier characteristic on Cu metallization was observed with ALD-TaN by BTS result in comparison to the conventional PVD-TaN.
{"title":"Characteristics of ALD-TaN thin films using a novel precursors for copper metallization","authors":"K. Choi, B. Kim, Sang woo Lee, Jong Myeong Lee","doi":"10.1109/IITC.2003.1219732","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219732","url":null,"abstract":"ALD-TaN thin films derived from tert-buthyIimidotrisdiethyl-amidotantalum (TBTDET) and tert-amylimidotrisdim-ethylamidotantalum (TAIMATA) precursors for the diffusion barrier in Cu interconnects were developed. The deposition rate of the ALD-TaN process was saturated at 0.4 /spl Aring/ /cycle in a temperature range between 200/spl deg/C and 250/spl deg/C with TBTDET and at 0.2 /spl Aring//cycle in a temperature range between 150/spl deg/C and 200/spl deg/C with TAIMATA. Both precursors provided roughly comparable film properties such as not only excellent conformality but also composition and structure characterized by XPS and XRD, respectively. ALD-TaN films obtained from above precursors yield low via resistance in aluminum interconnects. However, relatively high via resistance was resulted upon Cu integration as compared to PVD-TaN and Al metallization. The superior diffusion barrier characteristic on Cu metallization was observed with ALD-TaN by BTS result in comparison to the conventional PVD-TaN.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128855609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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