Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219705
R. Tadepalli, C. Thompson
Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnect test structures were created by thermocompression bonding, and the bond toughness was measured using a four-point bend test. The effects of bonding temperature, chamber ambient and copper thickness on bond quality were evaluated to optimize the bonding process. A new copper surface cleaning method using glacial acetic acid was employed to obtain high toughness bonds(/spl sim/17 J/m/sup 2/) at low bonding temperatures (<300/spl deg/C).
{"title":"Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits","authors":"R. Tadepalli, C. Thompson","doi":"10.1109/IITC.2003.1219705","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219705","url":null,"abstract":"Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnect test structures were created by thermocompression bonding, and the bond toughness was measured using a four-point bend test. The effects of bonding temperature, chamber ambient and copper thickness on bond quality were evaluated to optimize the bonding process. A new copper surface cleaning method using glacial acetic acid was employed to obtain high toughness bonds(/spl sim/17 J/m/sup 2/) at low bonding temperatures (<300/spl deg/C).","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219757
M. Tagami, H. Ohtake, Y. Hayashi, H. Miyamoto
Stability of organic low-k/Cu dual damascene interconnect under thermal cycle stresses is investigated, concluding that the thermal stability is improved by introducing Stress Control Layer (SCL) between metal-level inter-layer dielectric (ILD) film and via-level ILD film. The mismatches of the coefficient of thermal expansion (CTE) and the Young's modulus among the Cu, ILD and SCL films cause the stress voiding defects around the via-holes. In the case of CTE of SCL close to that of Cu, the via-stress opening is suppressed. When the modulus of SCL is closed to that of ILD, the voiding in the ILD around the via is suppressed. The selection of SCL material is a key part to improve the reliability of organic Low-k/Cu interconnect under severe thermal cycles.
{"title":"Effect of stress control layer (SCL) on via-stability in organic low-k/Cu dual damascene interconnects under thermal cycle stress","authors":"M. Tagami, H. Ohtake, Y. Hayashi, H. Miyamoto","doi":"10.1109/IITC.2003.1219757","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219757","url":null,"abstract":"Stability of organic low-k/Cu dual damascene interconnect under thermal cycle stresses is investigated, concluding that the thermal stability is improved by introducing Stress Control Layer (SCL) between metal-level inter-layer dielectric (ILD) film and via-level ILD film. The mismatches of the coefficient of thermal expansion (CTE) and the Young's modulus among the Cu, ILD and SCL films cause the stress voiding defects around the via-holes. In the case of CTE of SCL close to that of Cu, the via-stress opening is suppressed. When the modulus of SCL is closed to that of ILD, the voiding in the ILD around the via is suppressed. The selection of SCL material is a key part to improve the reliability of organic Low-k/Cu interconnect under severe thermal cycles.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219752
T. Furusawa, S. Machida, D. Ryuzaki, K. Sameshima, T. Ishida, K. Ishikawa, N. Miura, N. Konishi, T. Saito, H. Yamaguchi
A Cu/low-k dual-damascene process using a novel dissoluble hardmask material, AlO, is developed to suppress ashing-damage to porous/nonporous low-k SiOC. In this process, ArF-resist patterns are firstly transferred to a very thin, typically 30-nm-thick, AlO hardmask layer. After removing the resist, SiOC is patterned using the hardmask. The hardmask remaining after the etching is spontaneously removed during post-etch wet-cleaning. The line-to-line capacitance of 280-nm-pitch, 4-level interconnects using this process is reduced by 10% from that using a conventional resist-mask process.
{"title":"Novel dissoluble hardmask for damage-less Cu/low-k interconnect fabrication","authors":"T. Furusawa, S. Machida, D. Ryuzaki, K. Sameshima, T. Ishida, K. Ishikawa, N. Miura, N. Konishi, T. Saito, H. Yamaguchi","doi":"10.1109/IITC.2003.1219752","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219752","url":null,"abstract":"A Cu/low-k dual-damascene process using a novel dissoluble hardmask material, AlO, is developed to suppress ashing-damage to porous/nonporous low-k SiOC. In this process, ArF-resist patterns are firstly transferred to a very thin, typically 30-nm-thick, AlO hardmask layer. After removing the resist, SiOC is patterned using the hardmask. The hardmask remaining after the etching is spontaneously removed during post-etch wet-cleaning. The line-to-line capacitance of 280-nm-pitch, 4-level interconnects using this process is reduced by 10% from that using a conventional resist-mask process.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131048686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219700
C. Bruynseraede, D. Chiaradia, H. Wang, K. Maex
Starting from the concept of single-damascene Blech structures, a slit-test structure was devised for the assessment of mass transport at the Cu/barrier interface. Much more compatible with standard processing, the proposed slit-test structure easily matches the sensitivity to mass transport of traditional Blech structures. Finite Element Analysis indicates the electron flow in this structure to be concentrated at the Cu/barrier interface, making it electrically very sensitive to mass transport along this diffusion path. Electrical and physical failure analysis suggest a sensitivity high enough to enable wafer-level testing of interface diffusion at user conditions.
{"title":"EM-induced mass transport at the Cu/barrier interface: a new test structure for rapid assessment at user conditions","authors":"C. Bruynseraede, D. Chiaradia, H. Wang, K. Maex","doi":"10.1109/IITC.2003.1219700","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219700","url":null,"abstract":"Starting from the concept of single-damascene Blech structures, a slit-test structure was devised for the assessment of mass transport at the Cu/barrier interface. Much more compatible with standard processing, the proposed slit-test structure easily matches the sensitivity to mass transport of traditional Blech structures. Finite Element Analysis indicates the electron flow in this structure to be concentrated at the Cu/barrier interface, making it electrically very sensitive to mass transport along this diffusion path. Electrical and physical failure analysis suggest a sensitivity high enough to enable wafer-level testing of interface diffusion at user conditions.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126905908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219768
A. Fischer, A. von Glasow, S. Penka, F. Ungar
In this paper, we describe electromigration and stressvoiding mechanism in copper interconnects.
本文描述了铜互连中的电迁移和应力消除机制。
{"title":"Process optimization-the key to obtain highly reliable Cu interconnects","authors":"A. Fischer, A. von Glasow, S. Penka, F. Ungar","doi":"10.1109/IITC.2003.1219768","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219768","url":null,"abstract":"In this paper, we describe electromigration and stressvoiding mechanism in copper interconnects.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122267058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219772
Dae-Yong Kim, S.S. Wong
An infrared microscope and a convergent electron beam technique have been applied to detect and analyze the weak via in a Cu dual Damascene contact chain. It is shown that the early failure is due to cracking in the barrier metal layer, which opens up a fast diffusion path along the interface between the barrier metal and the dielectric. The subsequent opening and, in some cases, self-recovery of the via is also discussed. This early failure mode may impose severe limitation on the scalability of the dual Damascene structure.
{"title":"Mechanism for early failure in Cu dual damascene structure","authors":"Dae-Yong Kim, S.S. Wong","doi":"10.1109/IITC.2003.1219772","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219772","url":null,"abstract":"An infrared microscope and a convergent electron beam technique have been applied to detect and analyze the weak via in a Cu dual Damascene contact chain. It is shown that the early failure is due to cracking in the barrier metal layer, which opens up a fast diffusion path along the interface between the barrier metal and the dielectric. The subsequent opening and, in some cases, self-recovery of the via is also discussed. This early failure mode may impose severe limitation on the scalability of the dual Damascene structure.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219771
S. Matsumoto, A. Ishii, K. Tomita, K. Hashimoto, Y. Nishioka, M. Sekiguchi, A. Iwasaki, S. Isono, T. Satake, G. Okazaki, M. Fujisawa, Masahiro Matsumoto, S. Yamamoto, M. Matsuura
We have studied electromigration (EM) and stress-induced voiding (SV) behaviors based on our 90 nm-node Cu/low-k interconnect processes, and demonstrated successful improvement of the interconnect reliability. In EM study wide bimodal failure distribution was found only in the particular EM test structure. We identified that it caused by the lack of wettability between Cu and the barrier metal in the vias, and demonstrated that the optimization of the barrier metal thickness could suppress it. In SV behavior, we revealed a mechanism of the voiding under the vias that was due to the initial existence of the nuclei of the void before high temperature storage test. The failure mode was suppressed by optimizing preheat temperature of M2 barrier metal deposition.
{"title":"Reliability improvement of 9 nm-node Cu/low-k interconnects","authors":"S. Matsumoto, A. Ishii, K. Tomita, K. Hashimoto, Y. Nishioka, M. Sekiguchi, A. Iwasaki, S. Isono, T. Satake, G. Okazaki, M. Fujisawa, Masahiro Matsumoto, S. Yamamoto, M. Matsuura","doi":"10.1109/IITC.2003.1219771","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219771","url":null,"abstract":"We have studied electromigration (EM) and stress-induced voiding (SV) behaviors based on our 90 nm-node Cu/low-k interconnect processes, and demonstrated successful improvement of the interconnect reliability. In EM study wide bimodal failure distribution was found only in the particular EM test structure. We identified that it caused by the lack of wettability between Cu and the barrier metal in the vias, and demonstrated that the optimization of the barrier metal thickness could suppress it. In SV behavior, we revealed a mechanism of the voiding under the vias that was due to the initial existence of the nuclei of the void before high temperature storage test. The failure mode was suppressed by optimizing preheat temperature of M2 barrier metal deposition.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"61 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130912227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219715
J. Noguchi, T. Fujiwara, K. Sato, T. Nakamura, M. Kubo, S. Uno, K. Ishikawa, T. Saito, N. Konishi, Y. Yamada, T. Tamaru
A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.
{"title":"Simple self-aligned air-gap interconnect process with Cu/FSG structure","authors":"J. Noguchi, T. Fujiwara, K. Sato, T. Nakamura, M. Kubo, S. Uno, K. Ishikawa, T. Saito, N. Konishi, Y. Yamada, T. Tamaru","doi":"10.1109/IITC.2003.1219715","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219715","url":null,"abstract":"A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"737 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133630767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219745
J. Van Olmen, W. Wu, M. Van Hove, Y. Travaly, S. Brongersma, B. Eyckens, M. Maenhoudt, J. van Aelst, H. Struyf, S. Demuynck, Z. Tokei, I. Vervoort, B. Sijmus, I. Vos, I. Ciofi, M. Stucchi, K. Maex, F. Iacopi
This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.
{"title":"Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination","authors":"J. Van Olmen, W. Wu, M. Van Hove, Y. Travaly, S. Brongersma, B. Eyckens, M. Maenhoudt, J. van Aelst, H. Struyf, S. Demuynck, Z. Tokei, I. Vervoort, B. Sijmus, I. Vos, I. Ciofi, M. Stucchi, K. Maex, F. Iacopi","doi":"10.1109/IITC.2003.1219745","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219745","url":null,"abstract":"This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219707
R. Sarvari, J. Meindl
The change in the resistivity of a thin wire caused by anomalous skin effect (combined surface scattering and skin effect) is studied. The delay of a digital transmission line due to this effect is modeled. The results show that for a wire in the RC region surface scattering has the major effect on the delay whereas for a wire between the RC and RLC regions both surface scattering and skin effect should be considered.
{"title":"On the study of anomalous skin effect for GSI interconnections","authors":"R. Sarvari, J. Meindl","doi":"10.1109/IITC.2003.1219707","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219707","url":null,"abstract":"The change in the resistivity of a thin wire caused by anomalous skin effect (combined surface scattering and skin effect) is studied. The delay of a digital transmission line due to this effect is modeled. The results show that for a wire in the RC region surface scattering has the major effect on the delay whereas for a wire between the RC and RLC regions both surface scattering and skin effect should be considered.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116693806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：