Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219712
H. Miyoshi, H. Matsuo, Y. Oku, H. Tanaka, K. Yamada, N. Mikami, S. Takada, N. Hata, T. Kikkawa
We have demonstrated that the periodicity in pore structure increases the elastic modulus E with maintaining the dielectric constant k by analytical and numerical calculations. The periodic porous silica films having the hexagonal arrangement of circular cylindrical pores with k<2.0 and E>3 GPa is feasible at the porosity of 0.62 with the bulk material of k/sub b/=4.0 and E/sub b/>21 GPa. Calculation results have been confirmed with the experimental data by taking into account the experimental pore shape. The periodic porous silica films having the three-dimensional cubic structure of spherical pores with k<2.0 and E>3GPa is feasible at the porosity of 0.60 using the bulk material of k/sub b/=4.0 and E/sub b/>12 GPa.
{"title":"Theoretical analysis of ultra low-k porous films with periodic pore arrangement and high elastic modulus","authors":"H. Miyoshi, H. Matsuo, Y. Oku, H. Tanaka, K. Yamada, N. Mikami, S. Takada, N. Hata, T. Kikkawa","doi":"10.1109/IITC.2003.1219712","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219712","url":null,"abstract":"We have demonstrated that the periodicity in pore structure increases the elastic modulus E with maintaining the dielectric constant k by analytical and numerical calculations. The periodic porous silica films having the hexagonal arrangement of circular cylindrical pores with k<2.0 and E>3 GPa is feasible at the porosity of 0.62 with the bulk material of k/sub b/=4.0 and E/sub b/>21 GPa. Calculation results have been confirmed with the experimental data by taking into account the experimental pore shape. The periodic porous silica films having the three-dimensional cubic structure of spherical pores with k<2.0 and E>3GPa is feasible at the porosity of 0.60 using the bulk material of k/sub b/=4.0 and E/sub b/>12 GPa.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219743
K. Park, I. Kim, B. Suh, S. Choi, Wenhuai Song, Y. Wee, S. Lee, Jae-Sik Chung, J. Chung, S. Hah, Jeonghoon Ahn, K.T. Lee, H. Kang, K. Suh
An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.
{"title":"Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects","authors":"K. Park, I. Kim, B. Suh, S. Choi, Wenhuai Song, Y. Wee, S. Lee, Jae-Sik Chung, J. Chung, S. Hah, Jeonghoon Ahn, K.T. Lee, H. Kang, K. Suh","doi":"10.1109/IITC.2003.1219743","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219743","url":null,"abstract":"An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219718
M. Bakir, R.A. Villalaz, O. Ogunsola, T. Gaylord, P. Kohl, K. Martin, J. Meindl
Sea of Polymer Pillars (SoPP) provides highly integrated wafer-level optical and electrical Input/Output (I/O) interconnections for the die-to-module/board interconnection level. The advantages of this integrated interconnection technology include dual-mode I/O interconnections, high I/O density (>10/sup 5//cm/sup 2/), high performance, compliant electrical and optical interconnects, ease of assembly, wafer-level test compatibility, and ease of fabrication. The purpose of this paper is to extend the work developed by describing SoPP configurations, fabrication, and measurements.
{"title":"Sea of polymer pillars: dual-mode electrical-optical Input/Output interconnections","authors":"M. Bakir, R.A. Villalaz, O. Ogunsola, T. Gaylord, P. Kohl, K. Martin, J. Meindl","doi":"10.1109/IITC.2003.1219718","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219718","url":null,"abstract":"Sea of Polymer Pillars (SoPP) provides highly integrated wafer-level optical and electrical Input/Output (I/O) interconnections for the die-to-module/board interconnection level. The advantages of this integrated interconnection technology include dual-mode I/O interconnections, high I/O density (>10/sup 5//cm/sup 2/), high performance, compliant electrical and optical interconnects, ease of assembly, wafer-level test compatibility, and ease of fabrication. The purpose of this paper is to extend the work developed by describing SoPP configurations, fabrication, and measurements.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219751
C. Yeh, Y.C. Lu, T. Wu, H. Lu, C. Chen, H. Tao, M. Liang
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), /spl kappa/=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.
{"title":"Novel dual damascene patterning technology for ultra low-/spl kappa/ dielectrics","authors":"C. Yeh, Y.C. Lu, T. Wu, H. Lu, C. Chen, H. Tao, M. Liang","doi":"10.1109/IITC.2003.1219751","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219751","url":null,"abstract":"In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), /spl kappa/=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122748268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219713
H. Nakashima, N. Takagi, K. Masu
The prediction model for the interconnect length distribution (ILD) in LSIs with orthogonal interconnects based on Rent's empirical rule is extended to the prediction of ILD for the X Architecture containing diagonal interconnects and all-directional interconnects. The effectiveness of the X Architecture is evaluated based on the new prediction model.
{"title":"Derivation of interconnect length distribution in X architecture LSIs","authors":"H. Nakashima, N. Takagi, K. Masu","doi":"10.1109/IITC.2003.1219713","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219713","url":null,"abstract":"The prediction model for the interconnect length distribution (ILD) in LSIs with orthogonal interconnects based on Rent's empirical rule is extended to the prediction of ILD for the X Architecture containing diagonal interconnects and all-directional interconnects. The effectiveness of the X Architecture is evaluated based on the new prediction model.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131247195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219741
P. Wang, N. Tien, E. Kan
In this work, we demonstrate: (1) permalloy can be incorporated with planar transmission lines using CMOS compatible process. Patterning the permalloy structures can extend its application well into the microwave frequency range, (2) the transmission line characteristics do not change under up to 50 mA current excitations, (3) the patterned permalloy reduces the magnetic coupling between two adjacent transmission lines by approximately 10 dB. The demonstrated operation frequency range, current drivability and magnetic field shielding property show that the lines can be used for high-speed interconnect applications in CMOS technologies.
{"title":"Permalloy loaded transmission line for high-speed interconnects","authors":"P. Wang, N. Tien, E. Kan","doi":"10.1109/IITC.2003.1219741","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219741","url":null,"abstract":"In this work, we demonstrate: (1) permalloy can be incorporated with planar transmission lines using CMOS compatible process. Patterning the permalloy structures can extend its application well into the microwave frequency range, (2) the transmission line characteristics do not change under up to 50 mA current excitations, (3) the patterned permalloy reduces the magnetic coupling between two adjacent transmission lines by approximately 10 dB. The demonstrated operation frequency range, current drivability and magnetic field shielding property show that the lines can be used for high-speed interconnect applications in CMOS technologies.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134540369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219736
E. Kondoh, V. Vezin, K. Shigama, S. Sunada, K. Kubo, T. Ohta
Metal thin films for IC metallization are currently deposited either from vapor (PVD/CVD) or liquid (e.g. ECD). This paper reports critical bases for full IC metallization using only supercritical carbon dioxide (scCO/sub 2/) fluids as a deposition medium. High-aspect-ratio filling capability, (111)-preferential growth, low temperature deposition possibility, important roles of solvent capability of scCO/sub 2/ including F-less solid precursor utilization, and barrier metal deposition possibility are described.
{"title":"Paving the way for full-fluid IC metallization using supercritical carbon dioxide","authors":"E. Kondoh, V. Vezin, K. Shigama, S. Sunada, K. Kubo, T. Ohta","doi":"10.1109/IITC.2003.1219736","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219736","url":null,"abstract":"Metal thin films for IC metallization are currently deposited either from vapor (PVD/CVD) or liquid (e.g. ECD). This paper reports critical bases for full IC metallization using only supercritical carbon dioxide (scCO/sub 2/) fluids as a deposition medium. High-aspect-ratio filling capability, (111)-preferential growth, low temperature deposition possibility, important roles of solvent capability of scCO/sub 2/ including F-less solid precursor utilization, and barrier metal deposition possibility are described.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132625763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219719
J. Pallinti, S. Lakshminarayanan, W. Barth, P. Wright, M. Lu, S. Reder, L. Kwak, W. Catabay, D. Wang, F. Ho
An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed.
{"title":"An overview of stress free polishing of Cu with ultra low-k(k<2.0) films","authors":"J. Pallinti, S. Lakshminarayanan, W. Barth, P. Wright, M. Lu, S. Reder, L. Kwak, W. Catabay, D. Wang, F. Ho","doi":"10.1109/IITC.2003.1219719","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219719","url":null,"abstract":"An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"115 S147","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132904985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219721
E. Guyer, R. Dauskardt
The success of next generation interconnects relies to a large degree on the integration of low-k dielectric (LKD) materials capable of surviving chemical mechanical planarization (CMP). However, little is currently understood about the effect CMP slurry environments have on the reliability of these advanced dielectrics. Accordingly, the focus of this research was to characterize and model the effect of CMP solution chemistry on adhesion and subcritical debond growth in thin-film structures containing LKD materials for future generation devices.
{"title":"Effect of CMP slurry environments on subcritical crack growth in ultra low-k dielectric materials","authors":"E. Guyer, R. Dauskardt","doi":"10.1109/IITC.2003.1219721","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219721","url":null,"abstract":"The success of next generation interconnects relies to a large degree on the integration of low-k dielectric (LKD) materials capable of surviving chemical mechanical planarization (CMP). However, little is currently understood about the effect CMP slurry environments have on the reliability of these advanced dielectrics. Accordingly, the focus of this research was to characterize and model the effect of CMP solution chemistry on adhesion and subcritical debond growth in thin-film structures containing LKD materials for future generation devices.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"50 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134333529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219698
Y.L. Yang, L.P. Li, H. Ouyang, Y.C. Lu, H. Lu, C.H. Lin, K.C. Lin, S. Jang, M. Liang
A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400/spl deg/C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 /spl mu/m interline leakage, one million 0.13 /spl mu/m viachain via Rc and 0.12 /spl mu/m Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top CMP cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 /spl mu/m interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T/sub 63,/ of the Cu/LK(k=2.5) is predicted to be 4.56/spl times/10/sup 8/ yrs at 0.3 MV/cm and 125/spl deg/C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T/sub 0.1/ EM lifetimes for 0.12 /spl mu/m Cu line or 0.13 /spl mu/m via at 1 MA/cm2 and 110/spl deg/C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175/spl deg/C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.
{"title":"Fundamental, integration, and reliability of the 90 nm generation Cu/LK(k=2.5) damascene using a novel PECVD porous low-k dielectric film","authors":"Y.L. Yang, L.P. Li, H. Ouyang, Y.C. Lu, H. Lu, C.H. Lin, K.C. Lin, S. Jang, M. Liang","doi":"10.1109/IITC.2003.1219698","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219698","url":null,"abstract":"A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400/spl deg/C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 /spl mu/m interline leakage, one million 0.13 /spl mu/m viachain via Rc and 0.12 /spl mu/m Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top CMP cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 /spl mu/m interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T/sub 63,/ of the Cu/LK(k=2.5) is predicted to be 4.56/spl times/10/sup 8/ yrs at 0.3 MV/cm and 125/spl deg/C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T/sub 0.1/ EM lifetimes for 0.12 /spl mu/m Cu line or 0.13 /spl mu/m via at 1 MA/cm2 and 110/spl deg/C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175/spl deg/C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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