Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219753
N. Matsunaga, H. Yamaguchi, H. Shibata
Electric charge injection mechanism of plasma induced charging damage (PID) in a damascene interconnect process was investigated in detail. In the damascene interconnect process, PID is mainly induced in the deposition processes of Cu diffusion barrier film and inter layer dielectrics (ILD). We found that the antenna area dependence of the PID in the damascene interconnect process is not a simple relation to the top surface area of wiring. Since the charges are injected through the dielectric films on the wiring, effective antenna area which can collect the charges became larger than the area defined by the top surface area of the metal wiring.
{"title":"Spreading antenna effect of plasma induced charging damage in damascene interconnect process","authors":"N. Matsunaga, H. Yamaguchi, H. Shibata","doi":"10.1109/IITC.2003.1219753","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219753","url":null,"abstract":"Electric charge injection mechanism of plasma induced charging damage (PID) in a damascene interconnect process was investigated in detail. In the damascene interconnect process, PID is mainly induced in the deposition processes of Cu diffusion barrier film and inter layer dielectrics (ILD). We found that the antenna area dependence of the PID in the damascene interconnect process is not a simple relation to the top surface area of wiring. Since the charges are injected through the dielectric films on the wiring, effective antenna area which can collect the charges became larger than the area defined by the top surface area of the metal wiring.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134442838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219730
R. Li, W. Bomstad, J. Caserta, X. Guo, O. Kenneth
Integrated antennas for wireless connection between an integrated circuit and an off-chip antenna have been evaluated. At 23.5 GHz, the power transmission gain between an integrated 2-mm zigzag dipole antenna and an off-chip antenna increases by 5 dB and 10 dB when the substrate is changed from a 5-/spl Omega/-cm to a 20-/spl Omega/-cm silicon wafer, and from a 20-/spl Omega/-cm silicon wafer to a sapphire substrate, respectively. The antenna pair gain can be 20-30 dB higher than that for a pair of on-chip antennas, which leads to /spl sim/25 dB better sensitivity for a clock receiver working with an external antenna. This work also suggests that the integrated antenna length can be reduced below 1 mm.
{"title":"Evaluation of integrated antennas for wireless connection between an integrated circuit and an off-chip antenna","authors":"R. Li, W. Bomstad, J. Caserta, X. Guo, O. Kenneth","doi":"10.1109/IITC.2003.1219730","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219730","url":null,"abstract":"Integrated antennas for wireless connection between an integrated circuit and an off-chip antenna have been evaluated. At 23.5 GHz, the power transmission gain between an integrated 2-mm zigzag dipole antenna and an off-chip antenna increases by 5 dB and 10 dB when the substrate is changed from a 5-/spl Omega/-cm to a 20-/spl Omega/-cm silicon wafer, and from a 20-/spl Omega/-cm silicon wafer to a sapphire substrate, respectively. The antenna pair gain can be 20-30 dB higher than that for a pair of on-chip antennas, which leads to /spl sim/25 dB better sensitivity for a clock receiver working with an external antenna. This work also suggests that the integrated antenna length can be reduced below 1 mm.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219770
Ki-Don Lee, E. Ogawa, S. Yoon, Xia Lu, P. Ho
Electromigration (EM) statistics and critical current-density line-length product (jL)/sub c/ were investigated for Cu interconnects integrated with oxide, CVD low k, porous MSQ, organic polymer dielectrics. The EM activation energy was found to be about 0.8 to 1.0 eV, which is commonly associated with mass transport at the Cu/SiN/sub x/ cap-layer interface. The lower EM lifetime and threshold product (jL)/sub c/ can be attributed to a smaller back stress due to less thermomechanical confinement in the low k structures. The confinement effect can be expressed in terms of an effective modulus B to account for EM behavior and threshold products of low k structures. For all the ILDs studied, (jL)/sub c/ showed no temperature dependence but for the organic polymer, j dependence was observed.
{"title":"Electromigration threshold for Cu/low k interconnects","authors":"Ki-Don Lee, E. Ogawa, S. Yoon, Xia Lu, P. Ho","doi":"10.1109/IITC.2003.1219770","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219770","url":null,"abstract":"Electromigration (EM) statistics and critical current-density line-length product (jL)/sub c/ were investigated for Cu interconnects integrated with oxide, CVD low k, porous MSQ, organic polymer dielectrics. The EM activation energy was found to be about 0.8 to 1.0 eV, which is commonly associated with mass transport at the Cu/SiN/sub x/ cap-layer interface. The lower EM lifetime and threshold product (jL)/sub c/ can be attributed to a smaller back stress due to less thermomechanical confinement in the low k structures. The confinement effect can be expressed in terms of an effective modulus B to account for EM behavior and threshold products of low k structures. For all the ILDs studied, (jL)/sub c/ showed no temperature dependence but for the organic polymer, j dependence was observed.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219746
M. Matsuo, K. Kasai, Y. Okayama, K. Ishimaru, N. Matsunaga, H. Yamaguchi, N. Otsuka, N. Hayasaka
SRAM reliability impact and MOSFET electrical characteristics with copper (Cu) through-plug for three-dimensional (3-D) integration are examined and some degradation modes are inspected. Although the initial chip yield of chip-on-chip (COC) sample is comparable to references, the degradation occurs after high-temperature-storage (HTS) test. The degradation due to Cu diffusion could not be found, the mechanism of degradation is explainable in terms of plasma induced damage (PID) by the through-plug process. And it is found that the degradation is not crucial and it can be recovered by sinter process. Consequently, it is confirmed that the proposed COC process is practically effective and reliable. COC process is a promising solution for future high-performance system in package (SIP).
{"title":"Chip-on-chip technology with copper through-plug for 0.15 /spl mu/m SRAM","authors":"M. Matsuo, K. Kasai, Y. Okayama, K. Ishimaru, N. Matsunaga, H. Yamaguchi, N. Otsuka, N. Hayasaka","doi":"10.1109/IITC.2003.1219746","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219746","url":null,"abstract":"SRAM reliability impact and MOSFET electrical characteristics with copper (Cu) through-plug for three-dimensional (3-D) integration are examined and some degradation modes are inspected. Although the initial chip yield of chip-on-chip (COC) sample is comparable to references, the degradation occurs after high-temperature-storage (HTS) test. The degradation due to Cu diffusion could not be found, the mechanism of degradation is explainable in terms of plasma induced damage (PID) by the through-plug process. And it is found that the degradation is not crucial and it can be recovered by sinter process. Consequently, it is confirmed that the proposed COC process is practically effective and reliable. COC process is a promising solution for future high-performance system in package (SIP).","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124948759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219708
T. Tsui, R. Willecke, A. Mckerrow
Silicon carbide films containing either nitrogen or oxygen were integrated within a dual-level metal copper interconnect and characterized using Voltage Ramp and TDDB testing. Oxygen containing silicon carbide films were characterized by poor dielectric breakdown properties, but their performance improved with a short soak in ambient at elevated temperatures. This data suggests that oxygen containing silicon carbide films have poor moisture barrier properties. Similar evaluation of nitrogen containing silicon carbide films revealed materials properties that were more similar to those of silicon nitride. TDDB comparison of all three dielectric films is consistent with conclusions from the Voltage Ramp study.
{"title":"Effects of silicon carbide composition on dielectric barrier Voltage Ramp and TDDB reliability performance","authors":"T. Tsui, R. Willecke, A. Mckerrow","doi":"10.1109/IITC.2003.1219708","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219708","url":null,"abstract":"Silicon carbide films containing either nitrogen or oxygen were integrated within a dual-level metal copper interconnect and characterized using Voltage Ramp and TDDB testing. Oxygen containing silicon carbide films were characterized by poor dielectric breakdown properties, but their performance improved with a short soak in ambient at elevated temperatures. This data suggests that oxygen containing silicon carbide films have poor moisture barrier properties. Similar evaluation of nitrogen containing silicon carbide films revealed materials properties that were more similar to those of silicon nitride. TDDB comparison of all three dielectric films is consistent with conclusions from the Voltage Ramp study.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219747
R. Ho, K. Mai, M. Horowitz
We update prior wire scaling studies with data from the 2001 and 2002 ITRS roadmaps, extending out to the 13 nm node. Combining this data with more sophisticated wire models, over nine generations we see both local and global wires degrading relative to gates, by one and three orders of magnitude respectively. However, using repeaters for global wires as well as for the relatively few long local wires improves them significantly and makes local wires track gate delays. Inductive effects for delay are negligible, and inductive noise, given relatively lowcost design heuristics, is insignificant compared to capacitive noise. Wire aspect ratio sets capacitive coupling, and is limited to 2.2 in the ITRS roadmap to limit this noise. However, at this ratio designers already need to employ a number of noise countermeasures, whose effectiveness imply that noise need no longer be a principal reason to limit wire aspect ratios.
{"title":"Managing wire scaling: a circuit perspective","authors":"R. Ho, K. Mai, M. Horowitz","doi":"10.1109/IITC.2003.1219747","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219747","url":null,"abstract":"We update prior wire scaling studies with data from the 2001 and 2002 ITRS roadmaps, extending out to the 13 nm node. Combining this data with more sophisticated wire models, over nine generations we see both local and global wires degrading relative to gates, by one and three orders of magnitude respectively. However, using repeaters for global wires as well as for the relatively few long local wires improves them significantly and makes local wires track gate delays. Inductive effects for delay are negligible, and inductive noise, given relatively lowcost design heuristics, is insignificant compared to capacitive noise. Wire aspect ratio sets capacitive coupling, and is limited to 2.2 in the ITRS roadmap to limit this noise. However, at this ratio designers already need to employ a number of noise countermeasures, whose effectiveness imply that noise need no longer be a principal reason to limit wire aspect ratios.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128558020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219738
Y. Furukawa, R. Wolters, M. Patz
In this article a linewidth shrink of at least 20% due to deformation of a 193 nm-photo resist (PR) during etch is presented. The deformation of the resist takes place mainly at the top, resulting in an overhang and a decreased linewidth during single damascene (SD) etching. The effect of chemistry, pressure and power used in the dry etch process and PR coverage on PR deformation and sidewall slope of the hard mask (HM) has been investigated. Higher PR coverage and a polymerizing chemistry like Ar/CH/sub 2/F/sub 2//O/sub 2/ gives significant 193 nm PR deformation, resulting in a more sloped sidewall. An increase of the ion bombardment factor through a decreased pressure reduces PR deformation and sidewall slope slightly. 193 nm PR deformation begins already at the plasma ignition step; it depends on the masses of the reactant chemistry as ion bombardment source. The use of a N/sub 2/ plasma during ignition prevents 193 nm PR deformation during subsequent etching resulting in straight sidewall of HMs, even with polymerizing chemistry.
{"title":"Linewidth-narrowing due to 193 nm resist deformation during etch of spin-on low-k dielectrics","authors":"Y. Furukawa, R. Wolters, M. Patz","doi":"10.1109/IITC.2003.1219738","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219738","url":null,"abstract":"In this article a linewidth shrink of at least 20% due to deformation of a 193 nm-photo resist (PR) during etch is presented. The deformation of the resist takes place mainly at the top, resulting in an overhang and a decreased linewidth during single damascene (SD) etching. The effect of chemistry, pressure and power used in the dry etch process and PR coverage on PR deformation and sidewall slope of the hard mask (HM) has been investigated. Higher PR coverage and a polymerizing chemistry like Ar/CH/sub 2/F/sub 2//O/sub 2/ gives significant 193 nm PR deformation, resulting in a more sloped sidewall. An increase of the ion bombardment factor through a decreased pressure reduces PR deformation and sidewall slope slightly. 193 nm PR deformation begins already at the plasma ignition step; it depends on the masses of the reactant chemistry as ion bombardment source. The use of a N/sub 2/ plasma during ignition prevents 193 nm PR deformation during subsequent etching resulting in straight sidewall of HMs, even with polymerizing chemistry.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115293891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219748
Dongwen Gan, S. Yoon, P. Ho, P. Cresta, N. Singh, A. Bower, J. Leu, S. Shankar
In this study, we investigate the effect of passivation layer on mass transport by measuring stress relaxation in Cu damascene line structures. SiC and SiN/sub x/ passivation layers are investigated and compared with no passivation to examine the bonding effect on mass transport. The observed stress relaxation behavior is analyzed by a kinetic model considering the contribution to mass transport via various diffusion paths including the passivation interface. Results of this study show a significant effect due to the passivation layer that can be attributed to the interfacial chemistry.
{"title":"Effects of passivation layer on stress relaxation in Cu line structures","authors":"Dongwen Gan, S. Yoon, P. Ho, P. Cresta, N. Singh, A. Bower, J. Leu, S. Shankar","doi":"10.1109/IITC.2003.1219748","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219748","url":null,"abstract":"In this study, we investigate the effect of passivation layer on mass transport by measuring stress relaxation in Cu damascene line structures. SiC and SiN/sub x/ passivation layers are investigated and compared with no passivation to examine the bonding effect on mass transport. The observed stress relaxation behavior is analyzed by a kinetic model considering the contribution to mass transport via various diffusion paths including the passivation interface. Results of this study show a significant effect due to the passivation layer that can be attributed to the interfacial chemistry.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121538726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219716
M. Ikeda, J. Nakahira, Y. Iba, H. Kitada, N. Nishikawa, M. Miyajima, S. Fukuyama, N. Shimizu, K. Ikeda, T. Ohba, I. Sugiura, K. Suzuki, Y. Nakata, S. Doi, N. Awaji, E. Yano
A highly reliable nano-clustering silica (NCS) with low dielectric constant(k<2.3) and high elastic modulus (E=10 Gpa) for copper damascene process has been developed by controlling the size and distribution of pores in the NCS precursor. Using this material in a process compatible with the 90 nm technology node, we successfully demonstrated Cu wiring in NCS dielectrics.
{"title":"A highly reliable nano-clustering silica with low dielectric constant (k<2.3) and high elastic modulus (E=10 GPa) for copper damascene process","authors":"M. Ikeda, J. Nakahira, Y. Iba, H. Kitada, N. Nishikawa, M. Miyajima, S. Fukuyama, N. Shimizu, K. Ikeda, T. Ohba, I. Sugiura, K. Suzuki, Y. Nakata, S. Doi, N. Awaji, E. Yano","doi":"10.1109/IITC.2003.1219716","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219716","url":null,"abstract":"A highly reliable nano-clustering silica (NCS) with low dielectric constant(k<2.3) and high elastic modulus (E=10 Gpa) for copper damascene process has been developed by controlling the size and distribution of pores in the NCS precursor. Using this material in a process compatible with the 90 nm technology node, we successfully demonstrated Cu wiring in NCS dielectrics.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121671161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IITC.2003.1219693
The following topics were dealt: Process integration; reliability; interconnection systems; dielectrics; process control; interconnection systems I; CMP/planarisation; low-K; SOC; metallisation; dry process; metallisation; process integration; process integration II; reliability I; interconnection systems II; dielectrics; reliability II.
{"title":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","authors":"","doi":"10.1109/IITC.2003.1219693","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219693","url":null,"abstract":"The following topics were dealt: Process integration; reliability; interconnection systems; dielectrics; process control; interconnection systems I; CMP/planarisation; low-K; SOC; metallisation; dry process; metallisation; process integration; process integration II; reliability I; interconnection systems II; dielectrics; reliability II.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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