Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219726
K. Fujita, H. Miyajima, R. Nakata, N. Miyashita
High performance Low-k dielectric with porous structure (k=2.2) is realized by Electron-Beam (EB) cure technique, and applied to a 90 nm node Cu/Low-k multilevel damascene process. By EB curing, while maintaining a low k value, both mechanical strength and adhesion strength of lower interface have been improved 1.5 times respectively. This strengthening effect was actually confirmed as avoiding peeling by CMP process. In addition, introduction of EB cure technique reduced spin on dielectric (SOD) cure temperature and time, therefore the thermal budget was reduced drastically. It was also considered that this EB cure technology will be very effective in future 65 nm node devices.
{"title":"Notable improvement in porous low-k film properties using electron-beam cure method","authors":"K. Fujita, H. Miyajima, R. Nakata, N. Miyashita","doi":"10.1109/IITC.2003.1219726","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219726","url":null,"abstract":"High performance Low-k dielectric with porous structure (k=2.2) is realized by Electron-Beam (EB) cure technique, and applied to a 90 nm node Cu/Low-k multilevel damascene process. By EB curing, while maintaining a low k value, both mechanical strength and adhesion strength of lower interface have been improved 1.5 times respectively. This strengthening effect was actually confirmed as avoiding peeling by CMP process. In addition, introduction of EB cure technique reduced spin on dielectric (SOD) cure temperature and time, therefore the thermal budget was reduced drastically. It was also considered that this EB cure technology will be very effective in future 65 nm node devices.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116823769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219720
S. Kondo, S. Tokitoh, B. Yoon, A. Namiki, A. Sone, N. Ohashi, K. Misawa, S. Sone, H.J. Shin, T. Yoshie, K. Yoneda, M. Shimada, S. Ogawa, I. Matsumoto, N. Kobayashi
We developed a method of low-pressure CMP for the Cu damascene process on 300-mm wafers in order to prevent porous low-k film from being damaged. A new failure criterion, the time to CMP-induced delamination, was defined and found to be strongly dependent on the Young's modulus of the low-k film. In order to integrate porous low-k films into Cu damascene interconnects (k<2.5), a modulus of more than 8 GPa is required to suppress CMP-induced damage. He-plasma treatment before cap-CVD film deposition was also effective to improve low-k film adhesion. Because the time to delamination is inversely proportional to the polishing pressure, a high-removal-rate process is important even in low-pressure CMP. With a goal of integrating low-k materials (k<2.0) we investigated the feasibility of ultra-low pressure CMP (at 0.8 psi).
{"title":"Low-pressure CMP for reliable porous low-k/Cu integration","authors":"S. Kondo, S. Tokitoh, B. Yoon, A. Namiki, A. Sone, N. Ohashi, K. Misawa, S. Sone, H.J. Shin, T. Yoshie, K. Yoneda, M. Shimada, S. Ogawa, I. Matsumoto, N. Kobayashi","doi":"10.1109/IITC.2003.1219720","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219720","url":null,"abstract":"We developed a method of low-pressure CMP for the Cu damascene process on 300-mm wafers in order to prevent porous low-k film from being damaged. A new failure criterion, the time to CMP-induced delamination, was defined and found to be strongly dependent on the Young's modulus of the low-k film. In order to integrate porous low-k films into Cu damascene interconnects (k<2.5), a modulus of more than 8 GPa is required to suppress CMP-induced damage. He-plasma treatment before cap-CVD film deposition was also effective to improve low-k film adhesion. Because the time to delamination is inversely proportional to the polishing pressure, a high-removal-rate process is important even in low-pressure CMP. With a goal of integrating low-k materials (k<2.0) we investigated the feasibility of ultra-low pressure CMP (at 0.8 psi).","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114372669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219760
P. Kapur, K. Saraswat
We optimize the laser power and quantum well (QW) modulator metrics (contrast ratio (CR), insertion loss (IL)) to minimize power dissipation in short distance, modulator based, optical interconnects. We correspondingly quantify the optimal CR/IL modulator requirements as a function of various bit rates and a parameter dictated by voltage swing. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.
{"title":"Minimizing power dissipation in chip to chip optical interconnects using optimal modulators and laser power","authors":"P. Kapur, K. Saraswat","doi":"10.1109/IITC.2003.1219760","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219760","url":null,"abstract":"We optimize the laser power and quantum well (QW) modulator metrics (contrast ratio (CR), insertion loss (IL)) to minimize power dissipation in short distance, modulator based, optical interconnects. We correspondingly quantify the optimal CR/IL modulator requirements as a function of various bit rates and a parameter dictated by voltage swing. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219709
D. Maidenberg, W. Volksen, R. Miller, R. Dauskardt
Dielectric films (methylsilsesquioxane) with induced porosity were prepared and tested for their adhesion to metal and SiO/sub 2/ interfaces. Fracture mechanics techniques were employed to produce quantifiable and reproducible data without the confounding effects of residual stress relaxation. The effect of porosity on adhesion was shown to depend strongly on which interface was being measured. Remarkable increases in adhesion at the SiO/sub 2/ interface have been attributed to molecular bridging mechanisms activated by remnants of the pore-creating molecules.
{"title":"Effects of templating byproducts on adhesion of nanoporous dielectric films","authors":"D. Maidenberg, W. Volksen, R. Miller, R. Dauskardt","doi":"10.1109/IITC.2003.1219709","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219709","url":null,"abstract":"Dielectric films (methylsilsesquioxane) with induced porosity were prepared and tested for their adhesion to metal and SiO/sub 2/ interfaces. Fracture mechanics techniques were employed to produce quantifiable and reproducible data without the confounding effects of residual stress relaxation. The effect of porosity on adhesion was shown to depend strongly on which interface was being measured. Remarkable increases in adhesion at the SiO/sub 2/ interface have been attributed to molecular bridging mechanisms activated by remnants of the pore-creating molecules.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132104773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219751
C. Yeh, Y.C. Lu, T. Wu, H. Lu, C. Chen, H. Tao, M. Liang
In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), /spl kappa/=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.
{"title":"Novel dual damascene patterning technology for ultra low-/spl kappa/ dielectrics","authors":"C. Yeh, Y.C. Lu, T. Wu, H. Lu, C. Chen, H. Tao, M. Liang","doi":"10.1109/IITC.2003.1219751","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219751","url":null,"abstract":"In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), /spl kappa/=2.2, with 90 nm design rule and 193 nm lithography on the 300 mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65 nm generation and below without influenced by low-k materials and lithography technology.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122748268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219722
T. Harada, K. Kobayashi, M. Takahashi, K. Nii, A. Ikeda, T. Ueda, T. Yabu
The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.
{"title":"Reliability improvement of Cu interconnects by additional anneal between Cu CMP and barrier CMP","authors":"T. Harada, K. Kobayashi, M. Takahashi, K. Nii, A. Ikeda, T. Ueda, T. Yabu","doi":"10.1109/IITC.2003.1219722","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219722","url":null,"abstract":"The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115960612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219759
E. Beyne
The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.
{"title":"Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging","authors":"E. Beyne","doi":"10.1109/IITC.2003.1219759","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219759","url":null,"abstract":"The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219703
L. Arnaud, J.F. Guillaumond, O. Pesci, M. Fayolle, G. Reimbold
Electromigration studies showed that an activation energy Ea/spl sim/0.9 eV was obtained in Cu interconnects with SiOC as lateral dielectric for linewidths down to 0.28 /spl mu/m. Failure analysis showed similar EM diffusion path in Cu/SiOC interconnects in comparison to Cu/SiO/sub 2/ interconnects. Moreover electromigration lifetime is improved when a SiC cap layer is used: lifetime is increased in 0.4 /spl mu/m by a factor of 4 in comparison to SiN cap layer.
{"title":"Influence of dielectric layers on electromigration results in Cu interconnects","authors":"L. Arnaud, J.F. Guillaumond, O. Pesci, M. Fayolle, G. Reimbold","doi":"10.1109/IITC.2003.1219703","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219703","url":null,"abstract":"Electromigration studies showed that an activation energy Ea/spl sim/0.9 eV was obtained in Cu interconnects with SiOC as lateral dielectric for linewidths down to 0.28 /spl mu/m. Failure analysis showed similar EM diffusion path in Cu/SiOC interconnects in comparison to Cu/SiO/sub 2/ interconnects. Moreover electromigration lifetime is improved when a SiC cap layer is used: lifetime is increased in 0.4 /spl mu/m by a factor of 4 in comparison to SiN cap layer.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129681729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219712
H. Miyoshi, H. Matsuo, Y. Oku, H. Tanaka, K. Yamada, N. Mikami, S. Takada, N. Hata, T. Kikkawa
We have demonstrated that the periodicity in pore structure increases the elastic modulus E with maintaining the dielectric constant k by analytical and numerical calculations. The periodic porous silica films having the hexagonal arrangement of circular cylindrical pores with k<2.0 and E>3 GPa is feasible at the porosity of 0.62 with the bulk material of k/sub b/=4.0 and E/sub b/>21 GPa. Calculation results have been confirmed with the experimental data by taking into account the experimental pore shape. The periodic porous silica films having the three-dimensional cubic structure of spherical pores with k<2.0 and E>3GPa is feasible at the porosity of 0.60 using the bulk material of k/sub b/=4.0 and E/sub b/>12 GPa.
{"title":"Theoretical analysis of ultra low-k porous films with periodic pore arrangement and high elastic modulus","authors":"H. Miyoshi, H. Matsuo, Y. Oku, H. Tanaka, K. Yamada, N. Mikami, S. Takada, N. Hata, T. Kikkawa","doi":"10.1109/IITC.2003.1219712","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219712","url":null,"abstract":"We have demonstrated that the periodicity in pore structure increases the elastic modulus E with maintaining the dielectric constant k by analytical and numerical calculations. The periodic porous silica films having the hexagonal arrangement of circular cylindrical pores with k<2.0 and E>3 GPa is feasible at the porosity of 0.62 with the bulk material of k/sub b/=4.0 and E/sub b/>21 GPa. Calculation results have been confirmed with the experimental data by taking into account the experimental pore shape. The periodic porous silica films having the three-dimensional cubic structure of spherical pores with k<2.0 and E>3GPa is feasible at the porosity of 0.60 using the bulk material of k/sub b/=4.0 and E/sub b/>12 GPa.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219718
M. Bakir, R.A. Villalaz, O. Ogunsola, T. Gaylord, P. Kohl, K. Martin, J. Meindl
Sea of Polymer Pillars (SoPP) provides highly integrated wafer-level optical and electrical Input/Output (I/O) interconnections for the die-to-module/board interconnection level. The advantages of this integrated interconnection technology include dual-mode I/O interconnections, high I/O density (>10/sup 5//cm/sup 2/), high performance, compliant electrical and optical interconnects, ease of assembly, wafer-level test compatibility, and ease of fabrication. The purpose of this paper is to extend the work developed by describing SoPP configurations, fabrication, and measurements.
{"title":"Sea of polymer pillars: dual-mode electrical-optical Input/Output interconnections","authors":"M. Bakir, R.A. Villalaz, O. Ogunsola, T. Gaylord, P. Kohl, K. Martin, J. Meindl","doi":"10.1109/IITC.2003.1219718","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219718","url":null,"abstract":"Sea of Polymer Pillars (SoPP) provides highly integrated wafer-level optical and electrical Input/Output (I/O) interconnections for the die-to-module/board interconnection level. The advantages of this integrated interconnection technology include dual-mode I/O interconnections, high I/O density (>10/sup 5//cm/sup 2/), high performance, compliant electrical and optical interconnects, ease of assembly, wafer-level test compatibility, and ease of fabrication. The purpose of this paper is to extend the work developed by describing SoPP configurations, fabrication, and measurements.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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