Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219707
R. Sarvari, J. Meindl
The change in the resistivity of a thin wire caused by anomalous skin effect (combined surface scattering and skin effect) is studied. The delay of a digital transmission line due to this effect is modeled. The results show that for a wire in the RC region surface scattering has the major effect on the delay whereas for a wire between the RC and RLC regions both surface scattering and skin effect should be considered.
{"title":"On the study of anomalous skin effect for GSI interconnections","authors":"R. Sarvari, J. Meindl","doi":"10.1109/IITC.2003.1219707","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219707","url":null,"abstract":"The change in the resistivity of a thin wire caused by anomalous skin effect (combined surface scattering and skin effect) is studied. The delay of a digital transmission line due to this effect is modeled. The results show that for a wire in the RC region surface scattering has the major effect on the delay whereas for a wire between the RC and RLC regions both surface scattering and skin effect should be considered.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116693806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219760
P. Kapur, K. Saraswat
We optimize the laser power and quantum well (QW) modulator metrics (contrast ratio (CR), insertion loss (IL)) to minimize power dissipation in short distance, modulator based, optical interconnects. We correspondingly quantify the optimal CR/IL modulator requirements as a function of various bit rates and a parameter dictated by voltage swing. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.
{"title":"Minimizing power dissipation in chip to chip optical interconnects using optimal modulators and laser power","authors":"P. Kapur, K. Saraswat","doi":"10.1109/IITC.2003.1219760","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219760","url":null,"abstract":"We optimize the laser power and quantum well (QW) modulator metrics (contrast ratio (CR), insertion loss (IL)) to minimize power dissipation in short distance, modulator based, optical interconnects. We correspondingly quantify the optimal CR/IL modulator requirements as a function of various bit rates and a parameter dictated by voltage swing. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219709
D. Maidenberg, W. Volksen, R. Miller, R. Dauskardt
Dielectric films (methylsilsesquioxane) with induced porosity were prepared and tested for their adhesion to metal and SiO/sub 2/ interfaces. Fracture mechanics techniques were employed to produce quantifiable and reproducible data without the confounding effects of residual stress relaxation. The effect of porosity on adhesion was shown to depend strongly on which interface was being measured. Remarkable increases in adhesion at the SiO/sub 2/ interface have been attributed to molecular bridging mechanisms activated by remnants of the pore-creating molecules.
{"title":"Effects of templating byproducts on adhesion of nanoporous dielectric films","authors":"D. Maidenberg, W. Volksen, R. Miller, R. Dauskardt","doi":"10.1109/IITC.2003.1219709","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219709","url":null,"abstract":"Dielectric films (methylsilsesquioxane) with induced porosity were prepared and tested for their adhesion to metal and SiO/sub 2/ interfaces. Fracture mechanics techniques were employed to produce quantifiable and reproducible data without the confounding effects of residual stress relaxation. The effect of porosity on adhesion was shown to depend strongly on which interface was being measured. Remarkable increases in adhesion at the SiO/sub 2/ interface have been attributed to molecular bridging mechanisms activated by remnants of the pore-creating molecules.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132104773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219720
S. Kondo, S. Tokitoh, B. Yoon, A. Namiki, A. Sone, N. Ohashi, K. Misawa, S. Sone, H.J. Shin, T. Yoshie, K. Yoneda, M. Shimada, S. Ogawa, I. Matsumoto, N. Kobayashi
We developed a method of low-pressure CMP for the Cu damascene process on 300-mm wafers in order to prevent porous low-k film from being damaged. A new failure criterion, the time to CMP-induced delamination, was defined and found to be strongly dependent on the Young's modulus of the low-k film. In order to integrate porous low-k films into Cu damascene interconnects (k<2.5), a modulus of more than 8 GPa is required to suppress CMP-induced damage. He-plasma treatment before cap-CVD film deposition was also effective to improve low-k film adhesion. Because the time to delamination is inversely proportional to the polishing pressure, a high-removal-rate process is important even in low-pressure CMP. With a goal of integrating low-k materials (k<2.0) we investigated the feasibility of ultra-low pressure CMP (at 0.8 psi).
{"title":"Low-pressure CMP for reliable porous low-k/Cu integration","authors":"S. Kondo, S. Tokitoh, B. Yoon, A. Namiki, A. Sone, N. Ohashi, K. Misawa, S. Sone, H.J. Shin, T. Yoshie, K. Yoneda, M. Shimada, S. Ogawa, I. Matsumoto, N. Kobayashi","doi":"10.1109/IITC.2003.1219720","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219720","url":null,"abstract":"We developed a method of low-pressure CMP for the Cu damascene process on 300-mm wafers in order to prevent porous low-k film from being damaged. A new failure criterion, the time to CMP-induced delamination, was defined and found to be strongly dependent on the Young's modulus of the low-k film. In order to integrate porous low-k films into Cu damascene interconnects (k<2.5), a modulus of more than 8 GPa is required to suppress CMP-induced damage. He-plasma treatment before cap-CVD film deposition was also effective to improve low-k film adhesion. Because the time to delamination is inversely proportional to the polishing pressure, a high-removal-rate process is important even in low-pressure CMP. With a goal of integrating low-k materials (k<2.0) we investigated the feasibility of ultra-low pressure CMP (at 0.8 psi).","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114372669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219703
L. Arnaud, J.F. Guillaumond, O. Pesci, M. Fayolle, G. Reimbold
Electromigration studies showed that an activation energy Ea/spl sim/0.9 eV was obtained in Cu interconnects with SiOC as lateral dielectric for linewidths down to 0.28 /spl mu/m. Failure analysis showed similar EM diffusion path in Cu/SiOC interconnects in comparison to Cu/SiO/sub 2/ interconnects. Moreover electromigration lifetime is improved when a SiC cap layer is used: lifetime is increased in 0.4 /spl mu/m by a factor of 4 in comparison to SiN cap layer.
{"title":"Influence of dielectric layers on electromigration results in Cu interconnects","authors":"L. Arnaud, J.F. Guillaumond, O. Pesci, M. Fayolle, G. Reimbold","doi":"10.1109/IITC.2003.1219703","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219703","url":null,"abstract":"Electromigration studies showed that an activation energy Ea/spl sim/0.9 eV was obtained in Cu interconnects with SiOC as lateral dielectric for linewidths down to 0.28 /spl mu/m. Failure analysis showed similar EM diffusion path in Cu/SiOC interconnects in comparison to Cu/SiO/sub 2/ interconnects. Moreover electromigration lifetime is improved when a SiC cap layer is used: lifetime is increased in 0.4 /spl mu/m by a factor of 4 in comparison to SiN cap layer.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129681729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219729
P. Mazoyer, S. Blonkowski, F. Mondon, A. Farcy, J. Torres, G. Reimbold, F. Martin, J. Damlencourt, Y. Morand, N. Bicais, S. Descombes
An innovative 6 nm HfO/sub 2/ MIM capacitor was integrated in interconnect levels for eDRAM functions. HfO/sub 2/ layers or Al/sub 2/O/sub 3/-HfO/sub 2/ stacks were deposited by ALCVD/sup /spl reg//. Using damascene process with TiN electrodes, this method is fully compatible with copper interconnects technology. No high temperature annealing is required to obtain dielectric performances satisfying eDRAM needs: 30 fF per cell, low leakages and high reliability.
{"title":"MIM HfO/sub 2/ low leakage capacitors for eDRAM integration at interconnect levels","authors":"P. Mazoyer, S. Blonkowski, F. Mondon, A. Farcy, J. Torres, G. Reimbold, F. Martin, J. Damlencourt, Y. Morand, N. Bicais, S. Descombes","doi":"10.1109/IITC.2003.1219729","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219729","url":null,"abstract":"An innovative 6 nm HfO/sub 2/ MIM capacitor was integrated in interconnect levels for eDRAM functions. HfO/sub 2/ layers or Al/sub 2/O/sub 3/-HfO/sub 2/ stacks were deposited by ALCVD/sup /spl reg//. Using damascene process with TiN electrodes, this method is fully compatible with copper interconnects technology. No high temperature annealing is required to obtain dielectric performances satisfying eDRAM needs: 30 fF per cell, low leakages and high reliability.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219759
E. Beyne
The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.
{"title":"Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging","authors":"E. Beyne","doi":"10.1109/IITC.2003.1219759","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219759","url":null,"abstract":"The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219728
N. Nagaraj, M. Kulkarni, T. Bonifield, U. Narasimha, I. Hossain, C. Zabierek
This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.
{"title":"A systematic approach to interconnect modeling and process monitoring","authors":"N. Nagaraj, M. Kulkarni, T. Bonifield, U. Narasimha, I. Hossain, C. Zabierek","doi":"10.1109/IITC.2003.1219728","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219728","url":null,"abstract":"This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130463773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219764
T. Tatsumi, K. Nagahata, T. Saitoh, Y. Morita
We propose a mechanism and a prediction model for SiOCH etching. The surface reaction depends on both incident fluxes from plasma and material properties (film composition and density). The sensitivity of etch rate to the change in incident CF/sub x/ fluxes induces a narrow process window for the etching of SiOCH and porous SiOCH materials. Further cooperation between etching and other process engineers needs to be promoted to create a more reliable process module.
{"title":"SiOCH low-k etching: quantitative prediction of surface reaction","authors":"T. Tatsumi, K. Nagahata, T. Saitoh, Y. Morita","doi":"10.1109/IITC.2003.1219764","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219764","url":null,"abstract":"We propose a mechanism and a prediction model for SiOCH etching. The surface reaction depends on both incident fluxes from plasma and material properties (film composition and density). The sensitivity of etch rate to the change in incident CF/sub x/ fluxes induces a narrow process window for the etching of SiOCH and porous SiOCH materials. Further cooperation between etching and other process engineers needs to be promoted to create a more reliable process module.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130712125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219722
T. Harada, K. Kobayashi, M. Takahashi, K. Nii, A. Ikeda, T. Ueda, T. Yabu
The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.
{"title":"Reliability improvement of Cu interconnects by additional anneal between Cu CMP and barrier CMP","authors":"T. Harada, K. Kobayashi, M. Takahashi, K. Nii, A. Ikeda, T. Ueda, T. Yabu","doi":"10.1109/IITC.2003.1219722","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219722","url":null,"abstract":"The new technology which improves the reliability of Cu interconnects has been developed. In this technology, an anneal is carried out after a Cu CMP, followed by a barrier CMP and a p-SiN deposition. As a result, electromigration (EM) lifetime and stress-induced voiding (SIV) resistance have been improved drastically without the degradation of device performance and yield. Structural analyses suggest that the reliability improvement is realized by the reduction of tensile stress due to the stabilization of the Cu films and the minimization of the contact area of p-SiN/Cu interface due to the surface smoothing.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115960612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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