Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219750
K. Kikuchi, M. Takamiya, Y. Kudoh, K. Soejima, H. Honda, M. Mizuno, S. Yamamichi
A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology has been developed for low resistance power supply wirings in high-speed ULSIs. A thick Cu wiring fabricated by pulse periodic reverse electroplating achieves the good thickness uniformity without CMP process. A photosensitive resin as interlayer dielectric eliminates dry etching steps. Three layers of thick Cu wirings have been successfully fabricated on the top of a 0.13-/spl mu/m CMOS ULSI with three layers of 0.5 /spl mu/m-thick Al wiring. The total thick Cu wiring resistance is confirmed to be five times as small as that of the conventional two layers of 0.5-/spl mu/m-thick Al wirings. This simple technology is suitable for future low-cost ULSI global wirings.
{"title":"A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology with pulse periodic reverse electroplating and photosensitive resin","authors":"K. Kikuchi, M. Takamiya, Y. Kudoh, K. Soejima, H. Honda, M. Mizuno, S. Yamamichi","doi":"10.1109/IITC.2003.1219750","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219750","url":null,"abstract":"A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology has been developed for low resistance power supply wirings in high-speed ULSIs. A thick Cu wiring fabricated by pulse periodic reverse electroplating achieves the good thickness uniformity without CMP process. A photosensitive resin as interlayer dielectric eliminates dry etching steps. Three layers of thick Cu wirings have been successfully fabricated on the top of a 0.13-/spl mu/m CMOS ULSI with three layers of 0.5 /spl mu/m-thick Al wiring. The total thick Cu wiring resistance is confirmed to be five times as small as that of the conventional two layers of 0.5-/spl mu/m-thick Al wirings. This simple technology is suitable for future low-cost ULSI global wirings.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219765
R. Caluwaerts, M. Van Hove, G. Beyer, R. Hoofman, H. Struyf, G. Verheyden, J. Waeterloos, Z. Tokei, F. Iacopi, L. Carbonell, Q. Le, A. Das, I. Vos, S. Demuynck, K. Maex
The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.
{"title":"Post patterning meso porosity creation: a potential solution for pore sealing","authors":"R. Caluwaerts, M. Van Hove, G. Beyer, R. Hoofman, H. Struyf, G. Verheyden, J. Waeterloos, Z. Tokei, F. Iacopi, L. Carbonell, Q. Le, A. Das, I. Vos, S. Demuynck, K. Maex","doi":"10.1109/IITC.2003.1219765","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219765","url":null,"abstract":"The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219724
S. Ogawa, J. Shimanuki, M. Shimada, T. Nasuno, Y. Inoue, H. Mori
Transmission Electron Microscopy (TEM) has been applied to characterize pores in low-k films 3-dimentionally for the first time. To obtain the 3-dimentional shape of pores, TEM observations were operated in a stereo mode. The 3-dimentional TEM observations results showed that pores are not spherical but random in the shape and that pores do not exist uniformly but unevenly distribute in the low-k films and they tend to concentrate at the interface areas in examined SiC/low-k films stacks after commercially adequate cure treatments. The pores migrate in the low-k films during anneal at process temperatures such as 400 degrees C.
{"title":"3-Dimentional TEM stereo observation technology for characterization of pores in low-k film","authors":"S. Ogawa, J. Shimanuki, M. Shimada, T. Nasuno, Y. Inoue, H. Mori","doi":"10.1109/IITC.2003.1219724","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219724","url":null,"abstract":"Transmission Electron Microscopy (TEM) has been applied to characterize pores in low-k films 3-dimentionally for the first time. To obtain the 3-dimentional shape of pores, TEM observations were operated in a stereo mode. The 3-dimentional TEM observations results showed that pores are not spherical but random in the shape and that pores do not exist uniformly but unevenly distribute in the low-k films and they tend to concentrate at the interface areas in examined SiC/low-k films stacks after commercially adequate cure treatments. The pores migrate in the low-k films during anneal at process temperatures such as 400 degrees C.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219758
T. Tonegawa, M. Hiroi, K. Motoyama, K. Fujii, H. Miyamoto
The effect of impurity doping to Cu from Cu-alloy (CuSn and CuTi) seed layer on stress-induced voiding in Cu dual-damascene interconnects has been investigated. Significant suppression of both voiding inside vias and under vias was observed for CuSn. In addition, CuSn had 9 times the electromigration resistance of pure Cu, with available increments of sheet resistance. The difference in terms of reliability improvement between the doping materials is due to higher diffusivity of Sn into Cu in comparison to Ti. We have demonstrated high reliable Cu dual-damascene interconnects using high-diffusive dopant in the Cu-alloy seed layer.
{"title":"Suppression of bimodal stress-induced voiding using high-diffusive dopant from Cu-alloy seed layer","authors":"T. Tonegawa, M. Hiroi, K. Motoyama, K. Fujii, H. Miyamoto","doi":"10.1109/IITC.2003.1219758","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219758","url":null,"abstract":"The effect of impurity doping to Cu from Cu-alloy (CuSn and CuTi) seed layer on stress-induced voiding in Cu dual-damascene interconnects has been investigated. Significant suppression of both voiding inside vias and under vias was observed for CuSn. In addition, CuSn had 9 times the electromigration resistance of pure Cu, with available increments of sheet resistance. The difference in terms of reliability improvement between the doping materials is due to higher diffusivity of Sn into Cu in comparison to Ti. We have demonstrated high reliable Cu dual-damascene interconnects using high-diffusive dopant in the Cu-alloy seed layer.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127744216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219699
C. Jan, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, T. Hepburn, A. Jain, J. Jeong, T. Kielty, S. Kook, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, P. Wang, R. Wu, J. Xu, K. Zawadzki, S. Thompson, M. Bohr
This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.
{"title":"90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology","authors":"C. Jan, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, T. Hepburn, A. Jain, J. Jeong, T. Kielty, S. Kook, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, P. Wang, R. Wu, J. Xu, K. Zawadzki, S. Thompson, M. Bohr","doi":"10.1109/IITC.2003.1219699","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219699","url":null,"abstract":"This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126556920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219749
Jeong-Hoon Ahm, Kyung-Tae Lee, M. Jung, Yong-Jun Lee, B.J. Oh, Seong-Ho Liu, Yoon-hae Kim, Young-Wug Kim, K. Suh
Integration of MIM capacitors into 90 nm mixed-signal applications is demonstrated for the first time with the testing vehicle of AD converter using low-k (k=2.7) Cu dual damascene process. To obtain high resolution MIM capacitor, process such as electrode etching and CMP of upper Cu line was carefully optimized. The optimized process condition yields more reliable MIM capacitors with less parasitic components. The parasitic capacitance caused by surrounding upper metal interconnect gives significant effect for IMD thickness less than 300 nm. For parasitic capacitance-free MIM capacitor, a landing-metal type is suggested, and parasitic capacitance is reduced more than 60% compared with conventional capacitor structure.
{"title":"Integration of MIM capacitors with low-k/Cu process for 90 nm analog circuit applications","authors":"Jeong-Hoon Ahm, Kyung-Tae Lee, M. Jung, Yong-Jun Lee, B.J. Oh, Seong-Ho Liu, Yoon-hae Kim, Young-Wug Kim, K. Suh","doi":"10.1109/IITC.2003.1219749","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219749","url":null,"abstract":"Integration of MIM capacitors into 90 nm mixed-signal applications is demonstrated for the first time with the testing vehicle of AD converter using low-k (k=2.7) Cu dual damascene process. To obtain high resolution MIM capacitor, process such as electrode etching and CMP of upper Cu line was carefully optimized. The optimized process condition yields more reliable MIM capacitors with less parasitic components. The parasitic capacitance caused by surrounding upper metal interconnect gives significant effect for IMD thickness less than 300 nm. For parasitic capacitance-free MIM capacitor, a landing-metal type is suggested, and parasitic capacitance is reduced more than 60% compared with conventional capacitor structure.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126576469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219737
A. Matsushita, N. Ohashi, K. Inukai, H.J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, N. Kobayashi
Novel high-temperature (>150/spl deg/C ) ashing using mixture of H/sub 2/ and He gases (H/sub 2//He) was developed for low damage damascene fabrication of ultra low-k ILDs. Dependence of ashing characteristics on generated plasma configuration and temperature was investigated to optimize the process. Its applications to 320 nm pitch Cu/porous-MSQ (k=2.3) interconnects using 300 mm wafers showed no degradation in leakage currents and wiring capacitance. It is feasible for precise dual damascene etch using the conventional ArF photo resist (PR) mask process towards 65 nm technology node.
{"title":"Low damage ashing using H/sub 2//He plasma for porous ultra low-k","authors":"A. Matsushita, N. Ohashi, K. Inukai, H.J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, N. Kobayashi","doi":"10.1109/IITC.2003.1219737","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219737","url":null,"abstract":"Novel high-temperature (>150/spl deg/C ) ashing using mixture of H/sub 2/ and He gases (H/sub 2//He) was developed for low damage damascene fabrication of ultra low-k ILDs. Dependence of ashing characteristics on generated plasma configuration and temperature was investigated to optimize the process. Its applications to 320 nm pitch Cu/porous-MSQ (k=2.3) interconnects using 300 mm wafers showed no degradation in leakage currents and wiring capacitance. It is feasible for precise dual damascene etch using the conventional ArF photo resist (PR) mask process towards 65 nm technology node.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132376791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219725
H. Lee, C. Soles, D. Liu, B. Bauer, E. Lin, W. Wu
Methylsilsesquioxane based porous low-k dielectric films with different porogen loading have been characterized using X-ray porosimetry to determine their pore size distribution, average density, wall density and porosity. By varying the porogen content from 1 % to 30 %, the porosity and the average pore size changed from 12 % to 34 % and from 10 /spl Aring/ to 15 /spl Aring/ in radius, respectively. The wall density was found to be independent of the porogen content and it appeared that the porogen is not 100% effective in generating pores. Pore size of these samples was also obtained from small angle neutron scattering measurements and the results were found to be consistent with that from XRP.
{"title":"Structural characterization of methylsilsesquioxane-based porous low-k thin films using X-ray porosimetry","authors":"H. Lee, C. Soles, D. Liu, B. Bauer, E. Lin, W. Wu","doi":"10.1109/IITC.2003.1219725","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219725","url":null,"abstract":"Methylsilsesquioxane based porous low-k dielectric films with different porogen loading have been characterized using X-ray porosimetry to determine their pore size distribution, average density, wall density and porosity. By varying the porogen content from 1 % to 30 %, the porosity and the average pore size changed from 12 % to 34 % and from 10 /spl Aring/ to 15 /spl Aring/ in radius, respectively. The wall density was found to be independent of the porogen content and it appeared that the porogen is not 100% effective in generating pores. Pore size of these samples was also obtained from small angle neutron scattering measurements and the results were found to be consistent with that from XRP.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115529553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219769
M. Tada, Y. Harada, H. Ohtake, S. Saito, T. Onodera, Y. Hayashi
Reliably of Cu damascene interconnects (DDIs) using United Hard-mask and Cap (UHC) structure, which involves the same material for both Hard-mask and Cap layers is investigated. Line-to-line insulating reliabilities such as a leakage current, TZDB and TDDB are greatly improved by using the UHC structure even without any barrier metal layers, indicating that the interline leakage path is not in a bulk of the low-k dielectric but the interface between the Cap and the CMP-damaged Hard-mask. This new Cu dual damascene interconnect with UHC provides the interconnect reliability of future ULSIs with ultra-thin barrier metals toward a barrier-metal-free structure.
{"title":"Improvement of TDDB reliability in Cu damascene interconnect by using united hard-mask and Cap (UHC) structure","authors":"M. Tada, Y. Harada, H. Ohtake, S. Saito, T. Onodera, Y. Hayashi","doi":"10.1109/IITC.2003.1219769","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219769","url":null,"abstract":"Reliably of Cu damascene interconnects (DDIs) using United Hard-mask and Cap (UHC) structure, which involves the same material for both Hard-mask and Cap layers is investigated. Line-to-line insulating reliabilities such as a leakage current, TZDB and TDDB are greatly improved by using the UHC structure even without any barrier metal layers, indicating that the interline leakage path is not in a bulk of the low-k dielectric but the interface between the Cap and the CMP-damaged Hard-mask. This new Cu dual damascene interconnect with UHC provides the interconnect reliability of future ULSIs with ultra-thin barrier metals toward a barrier-metal-free structure.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115950127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219733
J.F. Guillaumond, L. Arnaud, T. Mourier, M. Fayolle, O. Pesci, G. Reimbold
The characterisation of the damascene copper line resistivity as a function of linewidth and temperature were carried out for sub 100 nm feature size and down to 4.2 K. Mayadas model for grain boundary and sidewall scattering was used to analyse experimental data. The model is found to be in good agreement with experiment. The difficulty to isolate the different electron scattering mechanisms is highlighted. However. all the results show clearly that ITRS roadmap present requirement will not be respected in a close future.
{"title":"Analysis of resistivity in nano-interconnect: full range (4.2-300 K) temperature characterization","authors":"J.F. Guillaumond, L. Arnaud, T. Mourier, M. Fayolle, O. Pesci, G. Reimbold","doi":"10.1109/IITC.2003.1219733","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219733","url":null,"abstract":"The characterisation of the damascene copper line resistivity as a function of linewidth and temperature were carried out for sub 100 nm feature size and down to 4.2 K. Mayadas model for grain boundary and sidewall scattering was used to analyse experimental data. The model is found to be in good agreement with experiment. The difficulty to isolate the different electron scattering mechanisms is highlighted. However. all the results show clearly that ITRS roadmap present requirement will not be respected in a close future.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128379159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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