Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494469
S. Santhosh
Identifying errors in HVDC converter and controlling HVDC system is presented in my paper. The easy and exact connoisseur system is neatly presented applying ANFIS (Acclimatized Neuro-Fuzzy Inference system. In both inversion and rectification mode faults are being identified when high voltage direct current with strong ac side and high voltage direct current with weak ac sides are available and incorporated fault identifier is developed replacing the old system of using individual error identifier in complete bridge converter. The conventionally used controller is PI which are in the existing HVDC systems is clearly operating good, they are prone to changes in system limits, holdups or other non-linearities in the system and endure from some limitations. ANFLBI and ANFLBC are the fuzzy logic supported error identifier and current controller respectively. ANFIS controller can function independently with arithmetical replica of the system and controlled input under interruption condition can be obtained without difficulty. My proposed system is easily combinable with error identifier, which can perk up active response of HVDC system. Quite a lot of digital replication results are obtainable to authenticate the process sketched in the paper.
{"title":"ANFIS based HVDC control and fault identification of HVDC converter","authors":"S. Santhosh","doi":"10.1109/ICETEEEM.2012.6494469","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494469","url":null,"abstract":"Identifying errors in HVDC converter and controlling HVDC system is presented in my paper. The easy and exact connoisseur system is neatly presented applying ANFIS (Acclimatized Neuro-Fuzzy Inference system. In both inversion and rectification mode faults are being identified when high voltage direct current with strong ac side and high voltage direct current with weak ac sides are available and incorporated fault identifier is developed replacing the old system of using individual error identifier in complete bridge converter. The conventionally used controller is PI which are in the existing HVDC systems is clearly operating good, they are prone to changes in system limits, holdups or other non-linearities in the system and endure from some limitations. ANFLBI and ANFLBC are the fuzzy logic supported error identifier and current controller respectively. ANFIS controller can function independently with arithmetical replica of the system and controlled input under interruption condition can be obtained without difficulty. My proposed system is easily combinable with error identifier, which can perk up active response of HVDC system. Quite a lot of digital replication results are obtainable to authenticate the process sketched in the paper.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"44 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128446726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494445
D. Nair, A. Nambiar, M. Raveendran, N. Mohan, S. Sampath
In this paper, the role of FACTS (Flexible AC Transmission System) devices in addressing various power quality issues has been studied. In FACTS, power electronic devices and their switching control schemes are used for improving the power flow in the transmission network and hence improve the power quality and reliability of the low-voltage distribution network. These devices can play a significant role in maximizing the power transmission capability of the transmission networkand providing high power quality at the point of common coupling (PCC) of the distribution system. The Distributed Static Compensator or DSTATCOM is a type of FACTS controller and has the function of reactive power compensation and harmonic mitigation. This paper discusses the use of synchronous detection algorithm for implementation of DSTATCOM for mitigation of harmonics. The dynamic performance is analyzed and verified through simulation.
{"title":"Mitigation of power quality issues using DSTATCOM","authors":"D. Nair, A. Nambiar, M. Raveendran, N. Mohan, S. Sampath","doi":"10.1109/ICETEEEM.2012.6494445","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494445","url":null,"abstract":"In this paper, the role of FACTS (Flexible AC Transmission System) devices in addressing various power quality issues has been studied. In FACTS, power electronic devices and their switching control schemes are used for improving the power flow in the transmission network and hence improve the power quality and reliability of the low-voltage distribution network. These devices can play a significant role in maximizing the power transmission capability of the transmission networkand providing high power quality at the point of common coupling (PCC) of the distribution system. The Distributed Static Compensator or DSTATCOM is a type of FACTS controller and has the function of reactive power compensation and harmonic mitigation. This paper discusses the use of synchronous detection algorithm for implementation of DSTATCOM for mitigation of harmonics. The dynamic performance is analyzed and verified through simulation.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494437
N. Nandhita, N. Gayathri
Improper handling of surgical instruments and sponges during the course of an operation on human body can prove to be fatal. This paper predominantly deals with prevention of misplacement of surgical elements by keeping account of both instruments and sponges being used, automatically rather than conventional manual checking. This is done by constructing a suitable casing with infra-red sensors to detect the presence of instruments. In the absence of any instrument for an abnormally long time period, a recorded-voice-message notifies the same. For sponges, a radio-frequency tag is attached. A check-in station and a check-out station, which are essentially antennae that read these RF-ID (Radio Frequency Identification) codes, are used. These are interfaced with software component that enables to monitor to number of instruments and sponges in the patients system at any instant. A GSM (Global System for Mobile communications) module at the end of the operation sends a message to the authority concerned in case of any discrepancy in the overall count. This system is expected to be more advantageous as it can track the surgical instruments periodically instead one final scan test for instruments. Traditional time-consuming and expensive methods like scanning the patient, taking X-ray post-operation, can be simply eliminated if this idea is implemented.
{"title":"Efficient life saving system to track surgical instruments","authors":"N. Nandhita, N. Gayathri","doi":"10.1109/ICETEEEM.2012.6494437","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494437","url":null,"abstract":"Improper handling of surgical instruments and sponges during the course of an operation on human body can prove to be fatal. This paper predominantly deals with prevention of misplacement of surgical elements by keeping account of both instruments and sponges being used, automatically rather than conventional manual checking. This is done by constructing a suitable casing with infra-red sensors to detect the presence of instruments. In the absence of any instrument for an abnormally long time period, a recorded-voice-message notifies the same. For sponges, a radio-frequency tag is attached. A check-in station and a check-out station, which are essentially antennae that read these RF-ID (Radio Frequency Identification) codes, are used. These are interfaced with software component that enables to monitor to number of instruments and sponges in the patients system at any instant. A GSM (Global System for Mobile communications) module at the end of the operation sends a message to the authority concerned in case of any discrepancy in the overall count. This system is expected to be more advantageous as it can track the surgical instruments periodically instead one final scan test for instruments. Traditional time-consuming and expensive methods like scanning the patient, taking X-ray post-operation, can be simply eliminated if this idea is implemented.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494494
P. Harsha, C. Subashini
In this project, a real-time embedded finger-vein recognition system for authentication on teller machine. The system is implemented on an embedded platform and equipped with a novel finger-vein recognition algorithm. The proposed system consists of three hardware modules: image acquisition module, embedded main board, and human machine communication module. The structure diagram of the system is, the image acquisition module is used to collect finger-vein images. The Embedded main board including the Microcontroller chip, memory (flash), and communication port is used to execute the finger-vein recognition algorithm and communicate with the peripheral device. The human machine communication module (LED or keyboard) is used to display recognition results and receive inputs from users. Our proposed system is intelligent security system. Here we developed teller machine concept. If finger vein matched, means transaction successful via GSM technology.
{"title":"A real time embedded novel finger-vein recognition system for authenticated on teller machine","authors":"P. Harsha, C. Subashini","doi":"10.1109/ICETEEEM.2012.6494494","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494494","url":null,"abstract":"In this project, a real-time embedded finger-vein recognition system for authentication on teller machine. The system is implemented on an embedded platform and equipped with a novel finger-vein recognition algorithm. The proposed system consists of three hardware modules: image acquisition module, embedded main board, and human machine communication module. The structure diagram of the system is, the image acquisition module is used to collect finger-vein images. The Embedded main board including the Microcontroller chip, memory (flash), and communication port is used to execute the finger-vein recognition algorithm and communicate with the peripheral device. The human machine communication module (LED or keyboard) is used to display recognition results and receive inputs from users. Our proposed system is intelligent security system. Here we developed teller machine concept. If finger vein matched, means transaction successful via GSM technology.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114056897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494518
A. Rao, Y. Obulesh, C. Babu
Multilevel converter technology has emerged as a very important alternative in the area of high-power medium-voltage energy control. Several topologies for multilevel inverters have been proposed over the years; the most popular cascaded H-bridge apart from other multilevel inverters is the capability of utilizing different dc voltages on the individual H-bridge cells which results in splitting the power conversion amongst higher-voltage lower-frequency and lower-voltage higher-frequency inverters. Considering the cascaded inverter to be one unit, it can be seen that a higher number of voltage levels are available for a given number of semiconductor devices. In this paper multilevel converters with different voltage levels are considered and simulation results are presented in terms of total harmonic distortion (THD). Finally generalized expression for highest order harmonic based on switching frequency and number of levels is derived.
{"title":"Analysis and effect of switching frequency and voltage levels on total harmonic distortion in multilevel inverters","authors":"A. Rao, Y. Obulesh, C. Babu","doi":"10.1109/ICETEEEM.2012.6494518","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494518","url":null,"abstract":"Multilevel converter technology has emerged as a very important alternative in the area of high-power medium-voltage energy control. Several topologies for multilevel inverters have been proposed over the years; the most popular cascaded H-bridge apart from other multilevel inverters is the capability of utilizing different dc voltages on the individual H-bridge cells which results in splitting the power conversion amongst higher-voltage lower-frequency and lower-voltage higher-frequency inverters. Considering the cascaded inverter to be one unit, it can be seen that a higher number of voltage levels are available for a given number of semiconductor devices. In this paper multilevel converters with different voltage levels are considered and simulation results are presented in terms of total harmonic distortion (THD). Finally generalized expression for highest order harmonic based on switching frequency and number of levels is derived.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116096269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494519
S. L. Sreedevi
The multilevel began with the three level converters. The elementary concept of a multilevel converter to achieve higher power to use a series of power semiconductor switches with several lower voltage dc source to perform the power conversion by synthesizing a staircase voltage waveform. However, the output voltage is smoother with a three level converter, in which the output voltage has three possible values. This results in smaller harmonics, but on the other hand it has more components and is more complex to control. In this paper, different three level inverter topologies and SPWM technique has been applied to formulate the switching pattern for three level inverter that minimize the harmonic distortion at the inverter output The 3 level inverter developed is used to power a 3 phase induction motor and Simulation result has discussed.
{"title":"Control strategy of three phase induction motor using three level inverter","authors":"S. L. Sreedevi","doi":"10.1109/ICETEEEM.2012.6494519","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494519","url":null,"abstract":"The multilevel began with the three level converters. The elementary concept of a multilevel converter to achieve higher power to use a series of power semiconductor switches with several lower voltage dc source to perform the power conversion by synthesizing a staircase voltage waveform. However, the output voltage is smoother with a three level converter, in which the output voltage has three possible values. This results in smaller harmonics, but on the other hand it has more components and is more complex to control. In this paper, different three level inverter topologies and SPWM technique has been applied to formulate the switching pattern for three level inverter that minimize the harmonic distortion at the inverter output The 3 level inverter developed is used to power a 3 phase induction motor and Simulation result has discussed.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128856691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494509
K. Shailesh, C. P. Kurian, S. Kini
Incredible long-life makes LED lighting systems a good long-term investment The higher capital cost is justified as there is long-term energy and maintenance cost savings. Operational requirements and materials used in manufacturing a of LEDs make then-failures distinctive compared to other microelectronics devices. Significant effort has gone into understanding of the failure modes and mechanisms and reliability of LED lighting. Although still very incomplete, our knowledge of the reliability issues relevant to LED lighting is increasing. This paper provides an overview of LED lighting failure modes and mechanisms that are commonly encountered. It focuses on the reliability issues of LED lighting.
{"title":"LED lighting reliability from a failure perspective","authors":"K. Shailesh, C. P. Kurian, S. Kini","doi":"10.1109/ICETEEEM.2012.6494509","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494509","url":null,"abstract":"Incredible long-life makes LED lighting systems a good long-term investment The higher capital cost is justified as there is long-term energy and maintenance cost savings. Operational requirements and materials used in manufacturing a of LEDs make then-failures distinctive compared to other microelectronics devices. Significant effort has gone into understanding of the failure modes and mechanisms and reliability of LED lighting. Although still very incomplete, our knowledge of the reliability issues relevant to LED lighting is increasing. This paper provides an overview of LED lighting failure modes and mechanisms that are commonly encountered. It focuses on the reliability issues of LED lighting.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494436
V. Elamaran, N. P. Reddy, K. Abhiram
Since the performance of portable electronic products increases continuously with demand, there is a need for low power digital VLSI design. Due to limited backup time of batteries, the operating time of portable electronic products is highly restricted. So the designers now concentrate on low power rather than the speed of the device or system. We implement a frequency divider (prescaler) using different flavors like conventional CMOS logic, pass transistor logic and transmission gate logic styles. Electronic Computer Aided Design (CAD) tools like Micro wind and a DSCH are used in our simulations by which the comparison of power in each style is provided. Micro wind is used a layout editor and DSCH (Digital Schematic) is used as a schematic editor. Results show that the pass transistor logic consumes less power with minimum area and good performance. We used BSTM4 MOSFET model in 0.12 μm for experimental results.
{"title":"Low power prescaler implementation in CMOS VLSI","authors":"V. Elamaran, N. P. Reddy, K. Abhiram","doi":"10.1109/ICETEEEM.2012.6494436","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494436","url":null,"abstract":"Since the performance of portable electronic products increases continuously with demand, there is a need for low power digital VLSI design. Due to limited backup time of batteries, the operating time of portable electronic products is highly restricted. So the designers now concentrate on low power rather than the speed of the device or system. We implement a frequency divider (prescaler) using different flavors like conventional CMOS logic, pass transistor logic and transmission gate logic styles. Electronic Computer Aided Design (CAD) tools like Micro wind and a DSCH are used in our simulations by which the comparison of power in each style is provided. Micro wind is used a layout editor and DSCH (Digital Schematic) is used as a schematic editor. Results show that the pass transistor logic consumes less power with minimum area and good performance. We used BSTM4 MOSFET model in 0.12 μm for experimental results.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133972917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494447
S. Sudhakar Reddy, S. Haider Nee Dey, S. Paul
This paper proposes a Particle Swarm Optimization based methodology for finding Optimal size and location of Distributed Generation and unbalanced Reactive power support for unbalanced three phase distribution network. The improvement in voltage profile and loss saving are presented. The proposed technique is tested on IEEE 37 node radial test feeder which is an actual feeder in California. The program is developed using MATLAB programming software. The results obtained show the effectiveness of the method for unbalanced network.
{"title":"Optimal size and location of Distributed Generation and KVAR support in unbalanced 3-Φ distribution system using PSO","authors":"S. Sudhakar Reddy, S. Haider Nee Dey, S. Paul","doi":"10.1109/ICETEEEM.2012.6494447","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494447","url":null,"abstract":"This paper proposes a Particle Swarm Optimization based methodology for finding Optimal size and location of Distributed Generation and unbalanced Reactive power support for unbalanced three phase distribution network. The improvement in voltage profile and loss saving are presented. The proposed technique is tested on IEEE 37 node radial test feeder which is an actual feeder in California. The program is developed using MATLAB programming software. The results obtained show the effectiveness of the method for unbalanced network.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131395288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICETEEEM.2012.6494522
A. D. Dhass, E. Natarajan, L. Ponnusamy
Connecting Photovoltaic (PV) cells to form an array can cause difficulties when the characteristics of the cells are not synchronized. Shunt Resistance (RSH) plays an important role in the performance of a PV. The leakage current resistance absorbs more current, due to that the current flows through the load circuit is reduced significantly. Increased leakage current among neighboring cells vary with electrical parameters to diminish the power output of the array and lead to cell degradation through localized heating of individual cells. Such problems often arise in effect of leakage current resistance or parallel resistance of a photovoltaic cell. In this paper, influence of a cell shunt resistance in a general photovoltaic cell on the fill factor (FF) has been analyzed. Variation in shunt resistance considerably changes the output power. A MATLAB program has been developed to study the variation in current-voltage (I-V) curve of the PV cell on the effect of shunt resistance. The algorithm for comparing the design data and experimental values of fill factor has identified the best efficiency solar cell with the effect of shunt resistance. In the I-V Curve the voltage value has been increased from 0.1 to 1.2V against the changes of shunt resistance value from 1 to 10Ω. In the shunt resistance-fill factor curve, the value of fill factor increases from 0.3 to 0.8 against the changes of shunt resistance value from 1 to 10Ω.
{"title":"Influence of shunt resistance on the performance of solar photovoltaic cell","authors":"A. D. Dhass, E. Natarajan, L. Ponnusamy","doi":"10.1109/ICETEEEM.2012.6494522","DOIUrl":"https://doi.org/10.1109/ICETEEEM.2012.6494522","url":null,"abstract":"Connecting Photovoltaic (PV) cells to form an array can cause difficulties when the characteristics of the cells are not synchronized. Shunt Resistance (RSH) plays an important role in the performance of a PV. The leakage current resistance absorbs more current, due to that the current flows through the load circuit is reduced significantly. Increased leakage current among neighboring cells vary with electrical parameters to diminish the power output of the array and lead to cell degradation through localized heating of individual cells. Such problems often arise in effect of leakage current resistance or parallel resistance of a photovoltaic cell. In this paper, influence of a cell shunt resistance in a general photovoltaic cell on the fill factor (FF) has been analyzed. Variation in shunt resistance considerably changes the output power. A MATLAB program has been developed to study the variation in current-voltage (I-V) curve of the PV cell on the effect of shunt resistance. The algorithm for comparing the design data and experimental values of fill factor has identified the best efficiency solar cell with the effect of shunt resistance. In the I-V Curve the voltage value has been increased from 0.1 to 1.2V against the changes of shunt resistance value from 1 to 10Ω. In the shunt resistance-fill factor curve, the value of fill factor increases from 0.3 to 0.8 against the changes of shunt resistance value from 1 to 10Ω.","PeriodicalId":213443,"journal":{"name":"2012 International Conference on Emerging Trends in Electrical Engineering and Energy Management (ICETEEEM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132719972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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