Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595713
V. Champac, A. Rubio, J. Figueras
The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and the quiescent current are estimated by means of analytical expressions. A good agreement is observed between the simple analytical expressions, simulations (SPICE) and experimental measures performed on defective circuits. It is shown that a floating gate transistor is not a stuck-open transistor and that significative values of quiescent current consumption may exist.
{"title":"Analysis of the floating gate defect in CMOS","authors":"V. Champac, A. Rubio, J. Figueras","doi":"10.1109/DFTVS.1993.595713","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595713","url":null,"abstract":"The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and the quiescent current are estimated by means of analytical expressions. A good agreement is observed between the simple analytical expressions, simulations (SPICE) and experimental measures performed on defective circuits. It is shown that a floating gate transistor is not a stuck-open transistor and that significative values of quiescent current consumption may exist.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125942969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595634
H. Al-Asaad, E. Manolakos
In order to maintain constant interconnection wire lengths between logically adjacent cells and avoid introducing additional tracks of buses and switches when linear arrays are extracted out of two-dimensional architectures with faulty processing elements, the spiral reconfiguration approach has been introduced. Its main drawback, relative to the tree and patching approaches, is that it leads to low harvesting. The authors introduce a two-phase reconfiguration strategy that drastically increases the harvesting ratio. The algorithm of the first phase achieves comparable harvesting to the previously proposed schemes, while it is simpler and can be implemented by on-chip logic. The algorithm of the second phase may complement any other scheme used during the first phase, and raises the harvesting ratio to levels that could be achieved by the much more involved tree approach.
{"title":"A two-phase reconfiguration strategy for extracting linear arrays out of two-dimensional architectures","authors":"H. Al-Asaad, E. Manolakos","doi":"10.1109/DFTVS.1993.595634","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595634","url":null,"abstract":"In order to maintain constant interconnection wire lengths between logically adjacent cells and avoid introducing additional tracks of buses and switches when linear arrays are extracted out of two-dimensional architectures with faulty processing elements, the spiral reconfiguration approach has been introduced. Its main drawback, relative to the tree and patching approaches, is that it leads to low harvesting. The authors introduce a two-phase reconfiguration strategy that drastically increases the harvesting ratio. The algorithm of the first phase achieves comparable harvesting to the previously proposed schemes, while it is simpler and can be implemented by on-chip logic. The algorithm of the second phase may complement any other scheme used during the first phase, and raises the harvesting ratio to levels that could be achieved by the much more involved tree approach.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126710214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595739
C. Stapper, J. Patrick, R. Rosner
Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips.
{"title":"Yield model for ASIC and processor chips","authors":"C. Stapper, J. Patrick, R. Rosner","doi":"10.1109/DFTVS.1993.595739","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595739","url":null,"abstract":"Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127348000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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