Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595817
X. Sun, M. Serra
The authors present a new testing scheme which merges concurrent checking and off-line BIST, sharing resources. A simple design template is described, together with an evaluation of area, fault coverage and latency.
{"title":"Design and implementation of a merged on-line and off-line self-testable architecture","authors":"X. Sun, M. Serra","doi":"10.1109/DFTVS.1993.595817","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595817","url":null,"abstract":"The authors present a new testing scheme which merges concurrent checking and off-line BIST, sharing resources. A simple design template is described, together with an evaluation of area, fault coverage and latency.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133411013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595782
M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.
{"title":"Layout level design for testability strategy applied to a CMOS cell library","authors":"M. Rullán, F. C. Blom, J. Oliver, C. Ferrer","doi":"10.1109/DFTVS.1993.595782","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595782","url":null,"abstract":"The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130450957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595772
E. Fujiwara, Masaharu Tanaka
The authors propose a large capacity high-speed file memory system implemented with wafer scale RAM which adopts novel defect-tolerant technique. The defective memory blocks in the wafer are repaired by switching with the spare ones based on set-associative mapping. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block address. The defective blocks remained even after applying the above two methods are repaired by using error correcting codes which also correct soft errors induced by alpha particles in an on-line operation. With using the proposed technique, the authors demonstrate a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.
{"title":"A defect-tolerant WSI file memory system using address permutation scheme for spare allocation","authors":"E. Fujiwara, Masaharu Tanaka","doi":"10.1109/DFTVS.1993.595772","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595772","url":null,"abstract":"The authors propose a large capacity high-speed file memory system implemented with wafer scale RAM which adopts novel defect-tolerant technique. The defective memory blocks in the wafer are repaired by switching with the spare ones based on set-associative mapping. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block address. The defective blocks remained even after applying the above two methods are repaired by using error correcting codes which also correct soft errors induced by alpha particles in an on-line operation. With using the proposed technique, the authors demonstrate a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595819
D. Wei, J. H. Kim, T. Rao
Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead.
最近，F. T. Assaad和S. Dutt(1992)提出了ABFT环境下浮点矩阵-矩阵乘法的混合校验和测试方法，这种方法可以大大提高误差覆盖率。然而，在矩阵乘法中涉及的浮点加法中，他们的方法仍然无法避免阈值测试，并且错误检测的次数随着数据动态范围的增加而减少，这并不完全令人满意。作者提出了一种有效的方法，称为并发浮点校验和(CFPC)测试，它以最小的时间延迟和硬件开销为浮点加法部分提供了非常令人信服的错误检测/纠正功能。
{"title":"Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays","authors":"D. Wei, J. H. Kim, T. Rao","doi":"10.1109/DFTVS.1993.595819","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595819","url":null,"abstract":"Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595824
Y. Hsu, E. Swartzlander
Time redundancy is an approach to achieve fault-tolerance without introducing excessive hardware that can be used in applications where time is not critical. The basic recomputing with duplication with comparison error-detecting adder propsed by Johnson was extended to perform error correction in both adders and multipliers. VLSI designs of time redundant error-detecting and error-correcting adders and multipliers are shown. Their hardware overhead is much lower than that of hardware redundancy approaches and the delay penalty is reasonable. Hence they are useful in systems where hardware complexity is the primary concern.
{"title":"VLSI concurrent error correcting adders and multipliers","authors":"Y. Hsu, E. Swartzlander","doi":"10.1109/DFTVS.1993.595824","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595824","url":null,"abstract":"Time redundancy is an approach to achieve fault-tolerance without introducing excessive hardware that can be used in applications where time is not critical. The basic recomputing with duplication with comparison error-detecting adder propsed by Johnson was extended to perform error correction in both adders and multipliers. VLSI designs of time redundant error-detecting and error-correcting adders and multipliers are shown. Their hardware overhead is much lower than that of hardware redundancy approaches and the delay penalty is reasonable. Hence they are useful in systems where hardware complexity is the primary concern.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131015486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595745
J. Crépeau, C. Thibeault, Y. Savaria
The authors study the influence of the line separation in a bus structure on a circuit cost. This structure was selected because it is easy to analyze and yet widely used. Using an analytical model, It is shown that an optimal design rule exists and how the gains obtained by using this optimal design rule depend on the bus length, the defect size distribution exponent and the clustering parameter. Some of the conclusions apply more generally to the problem of realizing design rules in an integrated circuit.
{"title":"Some results on yield and local design rule relaxation","authors":"J. Crépeau, C. Thibeault, Y. Savaria","doi":"10.1109/DFTVS.1993.595745","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595745","url":null,"abstract":"The authors study the influence of the line separation in a bus structure on a circuit cost. This structure was selected because it is easy to analyze and yet widely used. Using an analytical model, It is shown that an optimal design rule exists and how the gains obtained by using this optimal design rule depend on the bus length, the defect size distribution exponent and the clustering parameter. Some of the conclusions apply more generally to the problem of realizing design rules in an integrated circuit.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127045906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595609
H. Youn, Kyung Ook Lee
Parallel sorting is one of the most important computational problem. An efficient scheme for fault tolerant sorting is proposed, which is based on odd-even transposition sort with a linear array of processing elements (PEs). The faults in the array are tolerated as far as no more than a single compare-and-swap (CS) module fault exists in any three consecutive CS modules using the voting approach. The hardware overhead is basically an additional register and a voter per PE. The scheme can also be easily adapted to a two-dimensional processor arrays, using Shear sort. If the proposed approach is employed for only error detection, then multiple faults can be detected in each step of computation using only a simple XOR circuitry in each PE.
{"title":"Fault-tolerant sorting using VLSI processor arrays","authors":"H. Youn, Kyung Ook Lee","doi":"10.1109/DFTVS.1993.595609","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595609","url":null,"abstract":"Parallel sorting is one of the most important computational problem. An efficient scheme for fault tolerant sorting is proposed, which is based on odd-even transposition sort with a linear array of processing elements (PEs). The faults in the array are tolerated as far as no more than a single compare-and-swap (CS) module fault exists in any three consecutive CS modules using the voting approach. The hardware overhead is basically an additional register and a voter per PE. The scheme can also be easily adapted to a two-dimensional processor arrays, using Shear sort. If the proposed approach is employed for only error detection, then multiple faults can be detected in each step of computation using only a simple XOR circuitry in each PE.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124073708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595709
A. Kerek
Due to the high luminosity of LHC, the future accelerator of the European physics community, the number of events registered in a particle physics experiment is several order of magnitude higher than it is for the present generation detectors. This high countrate manifests also in the intense radiation in and around the experimental setup where the detector readout electronics is placed. This new radiation environment is compared to the radiation field in space where existing Rad Hard electronics is used. The radiation influence on electronics as well as different types of radiation hardened processes are discussed. A major expected contributor to the damage of semiconductors around LHC is the high flux of neutrons. The effect of this type of radiation, not present in space, is discussed.
{"title":"Front-end electronics in the radiation environment of LHC","authors":"A. Kerek","doi":"10.1109/DFTVS.1993.595709","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595709","url":null,"abstract":"Due to the high luminosity of LHC, the future accelerator of the European physics community, the number of events registered in a particle physics experiment is several order of magnitude higher than it is for the present generation detectors. This high countrate manifests also in the intense radiation in and around the experimental setup where the detector readout electronics is placed. This new radiation environment is compared to the radiation field in space where existing Rad Hard electronics is used. The radiation influence on electronics as well as different types of radiation hardened processes are discussed. A major expected contributor to the damage of semiconductors around LHC is the high flux of neutrons. The effect of this type of radiation, not present in space, is discussed.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595723
Hua Xue, C. Di, J. Jess
Based on the corner-stitching data structure, a geometrical approach to compute the critical area of a layout is presented. The run time of the proposed approach is linear to the number of patterns in a layout. Multilayer effect is taken into account so that the critical area computed for each mask layer is more accurate. The experimental results show that the method is promising for layout sensitivity analysis, yield estimation and realistic fault analysis.
{"title":"Fast multi-layer critical area computation","authors":"Hua Xue, C. Di, J. Jess","doi":"10.1109/DFTVS.1993.595723","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595723","url":null,"abstract":"Based on the corner-stitching data structure, a geometrical approach to compute the critical area of a layout is presented. The run time of the proposed approach is linear to the number of patterns in a layout. Multilayer effect is taken into account so that the critical area computed for each mask layer is more accurate. The experimental results show that the method is promising for layout sensitivity analysis, yield estimation and realistic fault analysis.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131646287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595730
E. Ferrati, Magneti Marelli
To obtain the reliability targets in automotive products is difficult. The environment for automotive products is comparable to military application while their cost has to compare favorably with consumer electronics. Automotive devices have to withstand wide electrical transients, strong thermal and mechanical stresses. In fact the main causes of failure are in almost perfect correlation with the above mentioned stresses. The partnership with semiconductor suppliers has the objective not only to guarantee the correct value of device parameters but also to define, at the design stage, the packaging size and all the other parameters which have a direct impact on component reliability. It is important to be able to design the set of reliability tests to be used to simulate the actual stress which the component will undergo during its life.
{"title":"The reliability of the integrated circuits in automotive industry","authors":"E. Ferrati, Magneti Marelli","doi":"10.1109/DFTVS.1993.595730","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595730","url":null,"abstract":"To obtain the reliability targets in automotive products is difficult. The environment for automotive products is comparable to military application while their cost has to compare favorably with consumer electronics. Automotive devices have to withstand wide electrical transients, strong thermal and mechanical stresses. In fact the main causes of failure are in almost perfect correlation with the above mentioned stresses. The partnership with semiconductor suppliers has the objective not only to guarantee the correct value of device parameters but also to define, at the design stage, the packaging size and all the other parameters which have a direct impact on component reliability. It is important to be able to design the set of reliability tests to be used to simulate the actual stress which the component will undergo during its life.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126510648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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