Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595750
F. Duvivier, M. Rivier, B. Burtschy, J. Charlot
The authors use a segmentation technique to correlate the chip yield of SRAMs with several parameters such as wafer number, chip radial and angular position on the wafer, lot number and manufacturing date. From a large database corresponding to a mature 1 /spl mu/m CMOS process, it is shown that the wafer to wafer variability is the most important variable explaining the spread of chip yield, followed by the radial position of the chip on the wafer. Variables such as angular position, lot number and data do not impact the yield variability.
{"title":"Use of a segmentation technique to analyze the variability of the yield of a mature CMOS SRAM","authors":"F. Duvivier, M. Rivier, B. Burtschy, J. Charlot","doi":"10.1109/DFTVS.1993.595750","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595750","url":null,"abstract":"The authors use a segmentation technique to correlate the chip yield of SRAMs with several parameters such as wafer number, chip radial and angular position on the wafer, lot number and manufacturing date. From a large database corresponding to a mature 1 /spl mu/m CMOS process, it is shown that the wafer to wafer variability is the most important variable explaining the spread of chip yield, followed by the radial position of the chip on the wafer. Variables such as angular position, lot number and data do not impact the yield variability.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595823
C. Metra, M. Favalli, P. Olivo, B. Riccò
The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view.
{"title":"A highly testable 1-out-of-3 CMOS checker","authors":"C. Metra, M. Favalli, P. Olivo, B. Riccò","doi":"10.1109/DFTVS.1993.595823","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595823","url":null,"abstract":"The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595657
J. Salinas, F. Lombardi
The authors examine the operation and a reconfiguration strategy for two-dimensional SIMD parallel architectures in the presence of manufacturing cluster defects and/or link defects when used for image processing. The proposed technique is based on a conceptual reconfiguration of processing elements by covering each large defect area with a set of fault-free elements, thus creating a loss of image resolution instead of a loss of image data. The proposed technique has been emulated on a 2048 PE MasPar architecture assuming both mesh connected elements (four-way connection) and eight-way connections.
作者研究了二维SIMD并行架构在用于图像处理时存在制造集群缺陷和/或链接缺陷的操作和重构策略。提出的技术是基于处理元素的概念重构，通过使用一组无故障元素覆盖每个大缺陷区域，从而造成图像分辨率的损失，而不是图像数据的损失。所提出的技术已经在2048 PE MasPar架构上进行了仿真，假设网格连接元素(四路连接)和八路连接。
{"title":"On the reconfigurable operation of arrays with defects for image processing","authors":"J. Salinas, F. Lombardi","doi":"10.1109/DFTVS.1993.595657","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595657","url":null,"abstract":"The authors examine the operation and a reconfiguration strategy for two-dimensional SIMD parallel architectures in the presence of manufacturing cluster defects and/or link defects when used for image processing. The proposed technique is based on a conceptual reconfiguration of processing elements by covering each large defect area with a set of fault-free elements, thus creating a loss of image resolution instead of a loss of image data. The proposed technique has been emulated on a 2048 PE MasPar architecture assuming both mesh connected elements (four-way connection) and eight-way connections.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595652
Hideo Ito
A defect-tolerant design for WSI interconnection networks (INs) is proposed, and three schemes with different switch structures are examined. Open defects on wiring lines and short defects between adjacent two wiring lines in links are assumed for defects in INs. The basic idea of the proposed design is to add redundant wiring lines and switches into each physical link. The three schemes are compared by evaluating yields when they are applied to hypercube networks. As a result, one scheme is superior to others, and an effect of defect-tolerant design by the scheme is effective and useful for six and eight dimensional hypercubes.
{"title":"A defect-tolerant design for WSI interconnection networks and its application to hypercube","authors":"Hideo Ito","doi":"10.1109/DFTVS.1993.595652","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595652","url":null,"abstract":"A defect-tolerant design for WSI interconnection networks (INs) is proposed, and three schemes with different switch structures are examined. Open defects on wiring lines and short defects between adjacent two wiring lines in links are assumed for defects in INs. The basic idea of the proposed design is to add redundant wiring lines and switches into each physical link. The three schemes are compared by evaluating yields when they are applied to hypercube networks. As a result, one scheme is superior to others, and an effect of defect-tolerant design by the scheme is effective and useful for six and eight dimensional hypercubes.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133421145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595604
R. Rochet, R. Leveugle, G. Saucier
Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.
{"title":"Analysis and comparison of fault tolerant FSM architecture based on SEC codes","authors":"R. Rochet, R. Leveugle, G. Saucier","doi":"10.1109/DFTVS.1993.595604","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595604","url":null,"abstract":"Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121400563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595607
Liang-Jin Lin, G. Redinbo
Adaptive FIR filters are widely used in a variety of modern digital signal processing application, and with the advancement in VLSI technology, it is now feasible to build fairly complicated multiprocessor systems which can provide the necessary computational power required by some highly demanding real-time signal processing applications. The increased computational power of such systems also makes fault tolerance an even more important issue that needs to be addressed carefully, because a single hardware failure can easily render the whole compuational results useless. Algorithm-based fault tolerance (ABFT), recently developed as an effective high level fault-tolerant technique, employs, in addition to the normal outputs, parity numbers that are related to the outputs. These parities can be used to concurrently detect, and in some cases correct, errors caused by hardware failures. A highly efficient implementation of the encoding scheme based on the weighted checksum code is proposed. It is particularly suitable for block adaptive signal processing, and the computational efficiency of this method is compared with that of the more general weighted checksum code.
{"title":"Block implementation of fault-tolerant LMS adaptive FIR filters","authors":"Liang-Jin Lin, G. Redinbo","doi":"10.1109/DFTVS.1993.595607","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595607","url":null,"abstract":"Adaptive FIR filters are widely used in a variety of modern digital signal processing application, and with the advancement in VLSI technology, it is now feasible to build fairly complicated multiprocessor systems which can provide the necessary computational power required by some highly demanding real-time signal processing applications. The increased computational power of such systems also makes fault tolerance an even more important issue that needs to be addressed carefully, because a single hardware failure can easily render the whole compuational results useless. Algorithm-based fault tolerance (ABFT), recently developed as an effective high level fault-tolerant technique, employs, in addition to the normal outputs, parity numbers that are related to the outputs. These parities can be used to concurrently detect, and in some cases correct, errors caused by hardware failures. A highly efficient implementation of the encoding scheme based on the weighted checksum code is proposed. It is particularly suitable for block adaptive signal processing, and the computational efficiency of this method is compared with that of the more general weighted checksum code.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125430606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595754
Z. Koren, I. Koren
The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip.
{"title":"Does the floorplan of a chip affect its yield?","authors":"Z. Koren, I. Koren","doi":"10.1109/DFTVS.1993.595754","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595754","url":null,"abstract":"The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595763
I. Wagner, I. Koren
The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A/sub c/) which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A/sub c/ efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm to solve it efficiently. This algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed defect sensitivity map that can assist a physical designer in improving the yield of his/her layout.
{"title":"An interactive yield estimator as a VLSI CAD tool","authors":"I. Wagner, I. Koren","doi":"10.1109/DFTVS.1993.595763","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595763","url":null,"abstract":"The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A/sub c/) which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A/sub c/ efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm to solve it efficiently. This algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed defect sensitivity map that can assist a physical designer in improving the yield of his/her layout.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"34 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123516777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595805
M. Bombana, G. Buonanno, P. Cavalloro, Fabrizio Ferrandi, D. Sciuto, G. Zaza
Testability analysis can be performed through classification of all possible simple interconnection topologies, definition of testability conditions on the function performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feedforward architectures are studied. Application of such an approach to irregular architectures with cycles (signal feedbacks) is presented.
{"title":"Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks","authors":"M. Bombana, G. Buonanno, P. Cavalloro, Fabrizio Ferrandi, D. Sciuto, G. Zaza","doi":"10.1109/DFTVS.1993.595805","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595805","url":null,"abstract":"Testability analysis can be performed through classification of all possible simple interconnection topologies, definition of testability conditions on the function performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feedforward architectures are studied. Application of such an approach to irregular architectures with cycles (signal feedbacks) is presented.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132531209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595827
P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira
High quality analog and mixed signal integrated circuits (ICs) require high quality testing. It is shown that test preparation, and test quality improvement of analog building blocks must be layout driven. For this, an IC defects-based analysis is used to study the impact of catastrophic faults on basic CMOS analog blocks. The impact on circuit behavior is analyzed for functional test and for i/sub DD/ power supply fault signatures. It is also demonstrated that a significant part of catastrophic faults cause out of specs performance, and may thus decrease the yield of the product, by an apparent parametric yield degradation. Finally, it is shown that layout level DFT (design for testability) can be rewardingly used to increase test confidence and product quality.
{"title":"Realistic fault analysis of CMOS analog building blocks","authors":"P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/DFTVS.1993.595827","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595827","url":null,"abstract":"High quality analog and mixed signal integrated circuits (ICs) require high quality testing. It is shown that test preparation, and test quality improvement of analog building blocks must be layout driven. For this, an IC defects-based analysis is used to study the impact of catastrophic faults on basic CMOS analog blocks. The impact on circuit behavior is analyzed for functional test and for i/sub DD/ power supply fault signatures. It is also demonstrated that a significant part of catastrophic faults cause out of specs performance, and may thus decrease the yield of the product, by an apparent parametric yield degradation. Finally, it is shown that layout level DFT (design for testability) can be rewardingly used to increase test confidence and product quality.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133274579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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