Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246334
A. Stoll, Jörg Biesenack, Steffen Rumler
A VHSIC hardware description language (VHDL) subset for high-level synthesis allowing a flexible timing specification of the circuit interface such that the optimization potential of classical scheduling and allocation techniques can be fully used is presented. The algorithmic circuit specification can be validated by a conventional VHDL simulator if the description style follows the proposed guidelines. This validation depends on the proper description style, but methods of timing specification allow an adequate low-level description of higher communication primitives such as the input and output commands.<>
{"title":"Flexible timing specification in a VHDL synthesis subset","authors":"A. Stoll, Jörg Biesenack, Steffen Rumler","doi":"10.1109/EURDAC.1992.246334","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246334","url":null,"abstract":"A VHSIC hardware description language (VHDL) subset for high-level synthesis allowing a flexible timing specification of the circuit interface such that the optimization potential of classical scheduling and allocation techniques can be fully used is presented. The algorithmic circuit specification can be validated by a conventional VHDL simulator if the description style follows the proposed guidelines. This validation depends on the proper description style, but methods of timing specification allow an adequate low-level description of higher communication primitives such as the input and output commands.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"41 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123207357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246198
S. Amadori, P. Coerezza
The design of complex systems requires a solid methodology in order to avoid dangerous anarchy during the design phase and to increase the overall quality of the final product. The presented methodology is founded on the use of VHSIC hardware description language (VHDL) as a common modeling language. The authors discuss modeling techniques in different areas: memory devices, ASICs, mu -processors and buses. An overview of some internally developed tools is presented.<>
{"title":"Design of complex systems with a VHDL based methodology","authors":"S. Amadori, P. Coerezza","doi":"10.1109/EURDAC.1992.246198","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246198","url":null,"abstract":"The design of complex systems requires a solid methodology in order to avoid dangerous anarchy during the design phase and to increase the overall quality of the final product. The presented methodology is founded on the use of VHSIC hardware description language (VHDL) as a common modeling language. The authors discuss modeling techniques in different areas: memory devices, ASICs, mu -processors and buses. An overview of some internally developed tools is presented.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124703762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246223
P. Gutberlet, Jens Müller, Heinrich Krämer, W. Rosenstiel
A main step in high-level synthesis is data-path synthesis consisting of allocation, scheduling and assignment. The authors present an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components (in type and number) fully automatically and supports a realistic area/time tradeoff. During this allocation a design space exploration is performed. The allocation is separated from the scheduling and assignment, allowing very efficient implementation.<>
{"title":"Automatic module allocation in high level synthesis","authors":"P. Gutberlet, Jens Müller, Heinrich Krämer, W. Rosenstiel","doi":"10.1109/EURDAC.1992.246223","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246223","url":null,"abstract":"A main step in high-level synthesis is data-path synthesis consisting of allocation, scheduling and assignment. The authors present an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components (in type and number) fully automatically and supports a realistic area/time tradeoff. During this allocation a design space exploration is performed. The allocation is separated from the scheduling and assignment, allowing very efficient implementation.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123882533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246197
M. Shahdad
The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility.<>
{"title":"1992 VHDL standardization overview","authors":"M. Shahdad","doi":"10.1109/EURDAC.1992.246197","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246197","url":null,"abstract":"The author reports on the VHSIC hardware description language (VHDL) standardization process. A brief description is given of language design objectives, areas of language change, language documentation, language validation, modeling, simulation, synthesis and upward compatibility.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126589678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246208
I. Pomeranz, L. Reddy, S. Reddy
A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, to obtain the highest fault coverage achieveable by every sequence; (2) during the simulation process, it is possible to determine the clocking scheme so as to minimize the number of different clocking schemes to be used with the sequence, without compromising the fault coverage; and (3) a path representation scheme that allows efficient access to path delay faults detected by previous tests is used. Experimental results are presented to demonstrate these features and their effectiveness.<>
{"title":"SPADES: a simulator for path delay faults in sequential circuits","authors":"I. Pomeranz, L. Reddy, S. Reddy","doi":"10.1109/EURDAC.1992.246208","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246208","url":null,"abstract":"A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, to obtain the highest fault coverage achieveable by every sequence; (2) during the simulation process, it is possible to determine the clocking scheme so as to minimize the number of different clocking schemes to be used with the sequence, without compromising the fault coverage; and (3) a path representation scheme that allows efficient access to path delay faults detected by previous tests is used. Experimental results are presented to demonstrate these features and their effectiveness.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246252
P. Agrawal, V. Agrawal, S. Seth
The authors provide a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. The path is considered to be sensitizable only if the corresponding stuck type fault is found detectable by a sequential circuit test generator. A depth-first analysis of circuit topology that determines all paths between primary inputs, primary outputs and flip-flops employs a partial path hierarchy. All paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that: (1) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer, and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20%.<>
{"title":"DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits","authors":"P. Agrawal, V. Agrawal, S. Seth","doi":"10.1109/EURDAC.1992.246252","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246252","url":null,"abstract":"The authors provide a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. The path is considered to be sensitizable only if the corresponding stuck type fault is found detectable by a sequential circuit test generator. A depth-first analysis of circuit topology that determines all paths between primary inputs, primary outputs and flip-flops employs a partial path hierarchy. All paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that: (1) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer, and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20%.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124386771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246195
Andrew Guyler
The changes to VHSIC hardware description language (VHDL) 1076-1987 for restandardization in 1992 are described. Emphasis is placed on the actual changes which have been made to the language. These are grouped into five topics: syntax and consistency; modeling; synthesis; packages; and visibility. The objective of the language design phase is to produce language change specifications (LCSs) that satisfy the requirements for change. Forty-eight LCSs were written, most of which provided input to the documentation team who were writing a new language reference manual (LRM).<>
{"title":"VHDL 1076-1992 languages changes","authors":"Andrew Guyler","doi":"10.1109/EURDAC.1992.246195","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246195","url":null,"abstract":"The changes to VHSIC hardware description language (VHDL) 1076-1987 for restandardization in 1992 are described. Emphasis is placed on the actual changes which have been made to the language. These are grouped into five topics: syntax and consistency; modeling; synthesis; packages; and visibility. The objective of the language design phase is to produce language change specifications (LCSs) that satisfy the requirements for change. Forty-eight LCSs were written, most of which provided input to the documentation team who were writing a new language reference manual (LRM).<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127857016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246226
A. Kunzmann
The author presents a new strategy to select a minimal test pattern set as a basis for test pattern generation by specific software or hardware modules. In contrast to other proposals this procedure is totally independent of the used test pattern generation algorithm. Based on the basic deterministic test pattern set, the test generation hardware can be easily realized. It is possible to show that the storage requirements could be drastically reduced on an average of more than 80% compared with the original deterministic test pattern sets.<>
{"title":"Generation of deterministic test patterns by minimal basic test sets","authors":"A. Kunzmann","doi":"10.1109/EURDAC.1992.246226","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246226","url":null,"abstract":"The author presents a new strategy to select a minimal test pattern set as a basis for test pattern generation by specific software or hardware modules. In contrast to other proposals this procedure is totally independent of the used test pattern generation algorithm. Based on the basic deterministic test pattern set, the test generation hardware can be easily realized. It is possible to show that the storage requirements could be drastically reduced on an average of more than 80% compared with the original deterministic test pattern sets.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134461008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246335
L. Ramachandran, Frank Vahid, Sanjiv Narayan, D. Gajski
Signals are a fundamental part of VHSIC hardware description language (VHDL) behavioral descriptions. Synthesis tools often inadequately address synthesis of global signals. The research presented eases the restrictions placed by existing synthesis systems on the VHDL shows that can be used to specify designs. In order to obtain functionally equivalent hardware from VHDL descriptions, it is essential to understand the semantics of VHDL constructs, especially for signals driven by several processes. The authors have introduced a conceptual hardware representation to explain the semantics of signals, ports, and resolution functions. Procedures to synthesize hardware for such constructs are given.<>
{"title":"Semantics and synthesis of signals in behavioral VHDL","authors":"L. Ramachandran, Frank Vahid, Sanjiv Narayan, D. Gajski","doi":"10.1109/EURDAC.1992.246335","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246335","url":null,"abstract":"Signals are a fundamental part of VHSIC hardware description language (VHDL) behavioral descriptions. Synthesis tools often inadequately address synthesis of global signals. The research presented eases the restrictions placed by existing synthesis systems on the VHDL shows that can be used to specify designs. In order to obtain functionally equivalent hardware from VHDL descriptions, it is essential to understand the semantics of VHDL constructs, especially for signals driven by several processes. The authors have introduced a conceptual hardware representation to explain the semantics of signals, ports, and resolution functions. Procedures to synthesize hardware for such constructs are given.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127869246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246180
S. Maginot
VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-purpose modeling language, whereas Verilog, UDL/I and M are more dedicated to IC modeling. The predefined environment of VHDL compares poorly to the implicit IC environment of other languages.<>
{"title":"Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M","authors":"S. Maginot","doi":"10.1109/EURDAC.1992.246180","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246180","url":null,"abstract":"VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-purpose modeling language, whereas Verilog, UDL/I and M are more dedicated to IC modeling. The predefined environment of VHDL compares poorly to the implicit IC environment of other languages.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115963930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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