Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246310
Kees Schot, M. Sim, P. M. Kist
ANT, a test harness for validation of a suite of design tools incorporated in a framework, is described. The harness is built upon the same framework used to support the tools and tests are modeled as hierarchical CAD objects. ANT is currently being employed for regression testing of the NELSIS (VLSI) CAD framework, and is available only for internal use at the university where it is being tested.<>
{"title":"ANT-A test harness for the NELSIS CAD system","authors":"Kees Schot, M. Sim, P. M. Kist","doi":"10.1109/EURDAC.1992.246310","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246310","url":null,"abstract":"ANT, a test harness for validation of a suite of design tools incorporated in a framework, is described. The harness is built upon the same framework used to support the tools and tests are modeled as hierarchical CAD objects. ANT is currently being employed for regression testing of the NELSIS (VLSI) CAD framework, and is available only for internal use at the university where it is being tested.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246189
Alain Fonkoua, J. Rouillard
The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized.<>
{"title":"VHDL intermediate format standardization activity: status and trends","authors":"Alain Fonkoua, J. Rouillard","doi":"10.1109/EURDAC.1992.246189","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246189","url":null,"abstract":"The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246228
T. Shimamoto, H. Hane, I. Shirakawa, S. Tsukiyama, S. Shinoda, Nobuyasu Yui, N. Nishiguchi
A distributed processing system dedicated to multilayer sea-of-gates (SOG) routing is described. The system is constructed of global and detailed routers, each based on distinct rip-up and rerouting procedures, so as to be run on a computer network composed of a number of workstations. Several implementation results attained for five-year SOG are also shown to reveal the practicality of the system. It is shown that CPU time with the same number of blocks decreases as the number of workstations increases. This implies an effect of distribution of the detailed routing. As the number of blocks increases, the wire length (i.e. the total number of edges used for routing in the grid graph) and the number of vias increase.<>
{"title":"A distributed routing system for multilayer SOG","authors":"T. Shimamoto, H. Hane, I. Shirakawa, S. Tsukiyama, S. Shinoda, Nobuyasu Yui, N. Nishiguchi","doi":"10.1109/EURDAC.1992.246228","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246228","url":null,"abstract":"A distributed processing system dedicated to multilayer sea-of-gates (SOG) routing is described. The system is constructed of global and detailed routers, each based on distinct rip-up and rerouting procedures, so as to be run on a computer network composed of a number of workstations. Several implementation results attained for five-year SOG are also shown to reveal the practicality of the system. It is shown that CPU time with the same number of blocks decreases as the number of workstations increases. This implies an effect of distribution of the detailed routing. As the number of blocks increases, the wire length (i.e. the total number of edges used for routing in the grid graph) and the number of vias increase.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132331867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246215
D. Feltham, J. Khare, Wojciech Maly
It is demonstrated that there is a relationship between the topology of the layout of the designed IC and the quality of testing. Based on this relationship, a testability cost function is developed for automated layout generation. The presented example indicates that a decrease in the testability objective function does correspond to an increase in the quality of testing without any penalty in terms of the cost of test generation. It is envisioned that such a function can be added as a component to the total objective function used by a modern placement and routing algorithm. Thus, using the presented techiques, it is possible to significantly improve the testability of a given circuit without increasing the cost of test generation.<>
{"title":"Design for testability view on placement and routing","authors":"D. Feltham, J. Khare, Wojciech Maly","doi":"10.1109/EURDAC.1992.246215","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246215","url":null,"abstract":"It is demonstrated that there is a relationship between the topology of the layout of the designed IC and the quality of testing. Based on this relationship, a testability cost function is developed for automated layout generation. The presented example indicates that a decrease in the testability objective function does correspond to an increase in the quality of testing without any penalty in terms of the cost of test generation. It is envisioned that such a function can be added as a component to the total objective function used by a modern placement and routing algorithm. Thus, using the presented techiques, it is possible to significantly improve the testability of a given circuit without increasing the cost of test generation.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121425564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246207
B. Becker, R. Hahn, Rolf Krieger
Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algorithm is very fast. The proposals and the improved data structure considerably enhance the performance of the standard algorithm.<>
{"title":"Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up","authors":"B. Becker, R. Hahn, Rolf Krieger","doi":"10.1109/EURDAC.1992.246207","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246207","url":null,"abstract":"Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algorithm is very fast. The proposals and the improved data structure considerably enhance the performance of the standard algorithm.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246182
V. Olive, R. Airiau, J. Bergé, A. Robert
The authors present a VHSIC hardware description language (VHDL) interface for a datapath generator. It introduces a method which is specific as well as library management for simulating and making synthesis. Implementing the data-path layout is discussed, and the specific use of VHDL for building the circuit layout is described. The entire interface has been specified in VHDL, demonstrating the possibility of extending the semantics of VHDL by adding particular attributes.<>
{"title":"Using VHDL for datapath synthesis","authors":"V. Olive, R. Airiau, J. Bergé, A. Robert","doi":"10.1109/EURDAC.1992.246182","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246182","url":null,"abstract":"The authors present a VHSIC hardware description language (VHDL) interface for a datapath generator. It introduces a method which is specific as well as library management for simulating and making synthesis. Implementing the data-path layout is discussed, and the specific use of VHDL for building the circuit layout is described. The entire interface has been specified in VHDL, demonstrating the possibility of extending the semantics of VHDL by adding particular attributes.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122476695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246265
H. Esbensen
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on a generalization of the two-dimensional bin packing problem. The genetic encoding of a macro cell placement and the corresponding genetic operators are described. The algorithm has been tested on MCNC benchmarks and the quality of the produced placements is comparable to the best published results.<>
{"title":"A genetic algorithm for macro cell placement","authors":"H. Esbensen","doi":"10.1109/EURDAC.1992.246265","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246265","url":null,"abstract":"A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on a generalization of the two-dimensional bin packing problem. The genetic encoding of a macro cell placement and the corresponding genetic operators are described. The algorithm has been tested on MCNC benchmarks and the quality of the produced placements is comparable to the best published results.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114793820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246246
F. Buijs
The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as bit-slices, just as in manual designs. Comparisons with existing tools show significant improvement.<>
{"title":"ALU synthesis from HDL descriptions to optimized multi-level logic","authors":"F. Buijs","doi":"10.1109/EURDAC.1992.246246","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246246","url":null,"abstract":"The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as bit-slices, just as in manual designs. Comparisons with existing tools show significant improvement.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123047300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246224
D. Crestani, A. Aguila, M. Gentil, P. Chardon, C. Durante
Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool.<>
{"title":"Automatic partitioning for deterministic test","authors":"D. Crestani, A. Aguila, M. Gentil, P. Chardon, C. Durante","doi":"10.1109/EURDAC.1992.246224","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246224","url":null,"abstract":"Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127352937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246260
H. Graeb, Claudia U. Wieser, K. Antreich
A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. Automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method are illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit proves the efficiency of the new approach.<>
{"title":"Design verification considering manufacturing tolerances by using worst-case distances","authors":"H. Graeb, Claudia U. Wieser, K. Antreich","doi":"10.1109/EURDAC.1992.246260","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246260","url":null,"abstract":"A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. Automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method are illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit proves the efficiency of the new approach.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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