Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246320
Daniel C. Liebisch, Adidev Jain
The authors outline the basic concepts used in the design management system of the JESSI common framework (JCF). The framework has been developed to aid designers in coping with complex designs existing in the world of CAD. Within the JCF, user, data, and tools that combine to form a design process are configured and executed in a single coherent fashion. Use of this methodology guarantees consistency of the design data. A versioning concept provides the freedom to try out various designs, prior to the selection of the best. The concepts of JCF can be used to save development time.<>
{"title":"JESSI common framework design management-the means to configuration and execution of the design process","authors":"Daniel C. Liebisch, Adidev Jain","doi":"10.1109/EURDAC.1992.246320","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246320","url":null,"abstract":"The authors outline the basic concepts used in the design management system of the JESSI common framework (JCF). The framework has been developed to aid designers in coping with complex designs existing in the world of CAD. Within the JCF, user, data, and tools that combine to form a design process are configured and executed in a single coherent fashion. Use of this methodology guarantees consistency of the design data. A versioning concept provides the freedom to try out various designs, prior to the selection of the best. The concepts of JCF can be used to save development time.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121444463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246329
G. Dedie
Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting this methodology are highly integrated with respect to all design steps and all design objects, rule driven and very fast to allow for short turnaround times, especially in the verification phase. The methodology and the tools allow the detection of all logic and timing errors before prototyping and provide for manufacturing and testability of the system. Challenges to the evolution of CAD tools and computer development methodologies are summarized.<>
{"title":"Challenges for CAD in computer development in the 1990s","authors":"G. Dedie","doi":"10.1109/EURDAC.1992.246329","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246329","url":null,"abstract":"Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting this methodology are highly integrated with respect to all design steps and all design objects, rule driven and very fast to allow for short turnaround times, especially in the verification phase. The methodology and the tools allow the detection of all logic and timing errors before prototyping and provide for manufacturing and testability of the system. Challenges to the evolution of CAD tools and computer development methodologies are summarized.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114349508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246183
C. Berthet, J. Rampon, L. Sponga
The problem of array objects in VHSIC hardware description language (VHDL) specifications for synthesis is considered. Experience shows that circuits obtained by synthesis tools are not as efficient as RAM macrocells. A new synthesis method is proposed that consists in mapping a VHDL array to a RAM primitive, together with a modification of the specification. The primitive is then mapped to a RAM generator of the THOMSON-TMS CSAM Library.<>
{"title":"Synthesis of VHDL arrays on RAM cells","authors":"C. Berthet, J. Rampon, L. Sponga","doi":"10.1109/EURDAC.1992.246183","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246183","url":null,"abstract":"The problem of array objects in VHSIC hardware description language (VHDL) specifications for synthesis is considered. Experience shows that circuits obtained by synthesis tools are not as efficient as RAM macrocells. A new synthesis method is proposed that consists in mapping a VHDL array to a RAM primitive, together with a modification of the specification. The primitive is then mapped to a RAM generator of the THOMSON-TMS CSAM Library.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114780876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246244
N. Wehn, H. Herpel, T. Hollstein, P. Poechmueller, M. Glesner
The application of high-level synthesis techniques onto a rapid-prototyping board is presented. The board is part of a design methodology that supports the development of embedded information processing units in mechatronic systems during early design phases. The spectrum of realizations ranges from single task software implementations on a single board computer to an ASIC emulation in a heterogeneous multiprocessor environment. Emphasis is on the automatic synthesis of hardware modules to be realized as ASICs. A synthesis environment is presented which automatically maps modules to be implemented as ASICs onto a rapid-prototyping board.<>
{"title":"High-level synthesis in a rapid-prototype environment for mechatronic systems","authors":"N. Wehn, H. Herpel, T. Hollstein, P. Poechmueller, M. Glesner","doi":"10.1109/EURDAC.1992.246244","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246244","url":null,"abstract":"The application of high-level synthesis techniques onto a rapid-prototyping board is presented. The board is part of a design methodology that supports the development of embedded information processing units in mechatronic systems during early design phases. The spectrum of realizations ranges from single task software implementations on a single board computer to an ASIC emulation in a heterogeneous multiprocessor environment. Emphasis is on the automatic synthesis of hardware modules to be realized as ASICs. A synthesis environment is presented which automatically maps modules to be implemented as ASICs onto a rapid-prototyping board.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246321
U. Hunzelmann, W. Wilkes, G. Schlageter
The tool interface which provides mechanisms for tools to implement their data handling facilities on the basis of a common data schema is a key element of a CAD framework. A tool interface which has been developed and implemented in the DASSY project is described. It decouples the CAD tools from the underlying database, and the chosen architecture with an integrated main memory database allows the adaptation of the tool interface to different databases.<>
{"title":"Design of a tool interface for integrated CAD-environments","authors":"U. Hunzelmann, W. Wilkes, G. Schlageter","doi":"10.1109/EURDAC.1992.246321","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246321","url":null,"abstract":"The tool interface which provides mechanisms for tools to implement their data handling facilities on the basis of a common data schema is a key element of a CAD framework. A tool interface which has been developed and implemented in the DASSY project is described. It decouples the CAD tools from the underlying database, and the chosen architecture with an integrated main memory database allows the adaptation of the tool interface to different databases.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246192
A. Pawlack
Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<>
{"title":"Selected aspects of component modeling","authors":"A. Pawlack","doi":"10.1109/EURDAC.1992.246192","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246192","url":null,"abstract":"Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124551304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246217
B. Becker, P. Molitor
The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, t/sub n/, the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area-minimal n-bit adder of the conditional-sum type with delay >
{"title":"A performance driven generator for efficient testable conditional-sum-adders","authors":"B. Becker, P. Molitor","doi":"10.1109/EURDAC.1992.246217","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246217","url":null,"abstract":"The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, t/sub n/, the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area-minimal n-bit adder of the conditional-sum type with delay <or=t/sub n/ (if such a circuit exists at all). The number of test vectors constructed is bounded by O(n/sup 2/). The running time of the generator itself is about c*n/sup 2/*t/sub n/ where c is a small constant.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124594986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246242
L. Hagen, A. Kahng, F. Kurdahi, C. Ramachandran
The complexity of circuit designs requires a top-down approach to layout synthesis. A good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout. The intrinsic Rent parameter of a netlist is defined as the minimum possible Rent parameter of any partitioning hierarchy for the netlist. Experimental results show that spectra-based ratio cut partitioning methods yield partitioning hierarchies with the lowest observed Rent parameter over all benchmarks and over all algorithms tested. For examples where the intrinsic Rent parameter is known, spectral ratio cut partitioning yields a Rent parameter essentially identical to this theoretical optimum. Additional theoretical results are provided to support the close relationship between spectral partitioning and the intrinsic Rent parameter.<>
{"title":"On the intrinsic Rent parameter and spectra-based partitioning methodologies","authors":"L. Hagen, A. Kahng, F. Kurdahi, C. Ramachandran","doi":"10.1109/EURDAC.1992.246242","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246242","url":null,"abstract":"The complexity of circuit designs requires a top-down approach to layout synthesis. A good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout. The intrinsic Rent parameter of a netlist is defined as the minimum possible Rent parameter of any partitioning hierarchy for the netlist. Experimental results show that spectra-based ratio cut partitioning methods yield partitioning hierarchies with the lowest observed Rent parameter over all benchmarks and over all algorithms tested. For examples where the intrinsic Rent parameter is known, spectral ratio cut partitioning yields a Rent parameter essentially identical to this theoretical optimum. Additional theoretical results are provided to support the close relationship between spectral partitioning and the intrinsic Rent parameter.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121255283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246314
Wolf-Dieter Tiedemann
The author reports on two high-level synthesis methods to derive controller implementations following different design paradigms from a common natural specification by timing diagrams. The first method automatically generates a Mealy automaton to be an input for a variety of excellent finite state machine (FSM) design algorithms. The second method supports an interactive bottom-up synthesis of asynchronous designs. Both methods are founded on the same mathematical basis, notably a process calculus. Due to their formal manifestation, every transformation (synthesis step) is verifiable. This leads to guaranteed correct implementations.<>
{"title":"An approach to multi-paradigm controller synthesis from timing diagram specifications","authors":"Wolf-Dieter Tiedemann","doi":"10.1109/EURDAC.1992.246314","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246314","url":null,"abstract":"The author reports on two high-level synthesis methods to derive controller implementations following different design paradigms from a common natural specification by timing diagrams. The first method automatically generates a Mealy automaton to be an input for a variety of excellent finite state machine (FSM) design algorithms. The second method supports an interactive bottom-up synthesis of asynchronous designs. Both methods are founded on the same mathematical basis, notably a process calculus. Due to their formal manifestation, every transformation (synthesis step) is verifiable. This leads to guaranteed correct implementations.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246266
S. Mohan, P. Mazumder
The typical computer-aided design environment today consists of a number of workstations connected by a high-speed local area network. The authors present a placement program that makes use of this distributed computing environment to achieve linear speedup without sacrificing the quality of the results obtained by the serial version of this program. The placement program is based on the genetic algorithm which is a heuristic search method inspired by biological evolution models. The authors describe the implementation of the placement program and detailed experimental studies of the behavior of the algorithm.<>
{"title":"Wolverines: standard cell placement on a network of workstations","authors":"S. Mohan, P. Mazumder","doi":"10.1109/EURDAC.1992.246266","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246266","url":null,"abstract":"The typical computer-aided design environment today consists of a number of workstations connected by a high-speed local area network. The authors present a placement program that makes use of this distributed computing environment to achieve linear speedup without sacrificing the quality of the results obtained by the serial version of this program. The placement program is based on the genetic algorithm which is a heuristic search method inspired by biological evolution models. The authors describe the implementation of the placement program and detailed experimental studies of the behavior of the algorithm.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122754290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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