Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246245
B. Falkowski, Ingo Schäfer, M. Perkowski
A theory has been developed to calculate the Rademacher-Walsh transform from a reduced representation (disjoint cubes) of incompletely specified Boolean functions. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. The program for the algorithms uses advantages of C language to speed up the execution. The comparison of different versions of the algorithm has been carried out. The algorithm successfully overcomes all drawbacks in the calculation of the transform from the design automation system based on spectral methods.<>
{"title":"Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions","authors":"B. Falkowski, Ingo Schäfer, M. Perkowski","doi":"10.1109/EURDAC.1992.246245","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246245","url":null,"abstract":"A theory has been developed to calculate the Rademacher-Walsh transform from a reduced representation (disjoint cubes) of incompletely specified Boolean functions. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. The program for the algorithms uses advantages of C language to speed up the execution. The comparison of different versions of the algorithm has been carried out. The algorithm successfully overcomes all drawbacks in the calculation of the transform from the design automation system based on spectral methods.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121556707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246216
B. Becker, R. Drechsler
A log(n)-time robust path-delay-fault (PDF) testable adder is presented. The adder is a modified version of a conditional carry adder (CCA). An optimal test set of size Theta (n/sup 2/*log(n)) is constructed. The realization of a selftest for the adder is discussed; an algorithm of complexity O(n/sup 3/) for the generation of a complete test set is used. A short hardware analysis of the CCA and its robust PDF-modification are presented.<>
{"title":"A time optimal robust path-delay-fault self-testable adder","authors":"B. Becker, R. Drechsler","doi":"10.1109/EURDAC.1992.246216","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246216","url":null,"abstract":"A log(n)-time robust path-delay-fault (PDF) testable adder is presented. The adder is a modified version of a conditional carry adder (CCA). An optimal test set of size Theta (n/sup 2/*log(n)) is constructed. The realization of a selftest for the adder is discussed; an algorithm of complexity O(n/sup 3/) for the generation of a complete test set is used. A short hardware analysis of the CCA and its robust PDF-modification are presented.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122115413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246184
W. Ecker, Sabine März
The authors propose to exploit the VHSIC hardware description language (VHDL) subtype concept for formulating ranges for design constraints which could be used as inputs for synthesis tools. The proposed method relies on interpreting the range of a VHDL constant's type as a range specification for a design constraint. Presynthesis simulation is done with an estimated value inside the specified range. Postsynthesis simulation in order to check functionality as well as consistency with design constraints is performed by using the actual values resulting from synthesis.<>
{"title":"Subtype concept of VHDL for synthesis constraints","authors":"W. Ecker, Sabine März","doi":"10.1109/EURDAC.1992.246184","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246184","url":null,"abstract":"The authors propose to exploit the VHSIC hardware description language (VHDL) subtype concept for formulating ranges for design constraints which could be used as inputs for synthesis tools. The proposed method relies on interpreting the range of a VHDL constant's type as a range specification for a design constraint. Presynthesis simulation is done with an estimated value inside the specified range. Postsynthesis simulation in order to check functionality as well as consistency with design constraints is performed by using the actual values resulting from synthesis.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246251
A. Kayssi, K. Sakallah
A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such parameters as transistor sizes, capacitive loading, fanout, and input switching time. Calculations based on the derived macromodel show excellent agreement with circuit simulation at two to three orders of magnitude savings in computation time.<>
{"title":"Delay macromodels for the timing analysis of GaAs DCFL","authors":"A. Kayssi, K. Sakallah","doi":"10.1109/EURDAC.1992.246251","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246251","url":null,"abstract":"A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such parameters as transistor sizes, capacitive loading, fanout, and input switching time. Calculations based on the derived macromodel show excellent agreement with circuit simulation at two to three orders of magnitude savings in computation time.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122883277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246213
Haigeng Wang, N. Dutt, A. Nicolau
Linear difference equations involving recurrences are fundamental equations that describe many important signal processing applications. For many high sample rate digital filter applications, it is necessary to effectively parallelize the linear difference equations used to describe digital filters. This is difficult because of the recurrences inherent in the data dependences. The authors present a novel approach, harmonic scheduling, that exploits parallelism in these recurrences beyond loop-carried dependencies, and which generates optimal schedules for parallel evaluation of linear difference equations with resource constraints. This approach also enables the derivation of a parallel schedule with minimum control overhead, given an execution time with resource constraints. A harmonic scheduling algorithm is presented to generate optimal schedules for digital filters described by second-order difference equations with resource constraints.<>
{"title":"Harmonic scheduling of linear recurrences for digital filter design","authors":"Haigeng Wang, N. Dutt, A. Nicolau","doi":"10.1109/EURDAC.1992.246213","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246213","url":null,"abstract":"Linear difference equations involving recurrences are fundamental equations that describe many important signal processing applications. For many high sample rate digital filter applications, it is necessary to effectively parallelize the linear difference equations used to describe digital filters. This is difficult because of the recurrences inherent in the data dependences. The authors present a novel approach, harmonic scheduling, that exploits parallelism in these recurrences beyond loop-carried dependencies, and which generates optimal schedules for parallel evaluation of linear difference equations with resource constraints. This approach also enables the derivation of a parallel schedule with minimum control overhead, given an execution time with resource constraints. A harmonic scheduling algorithm is presented to generate optimal schedules for digital filters described by second-order difference equations with resource constraints.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246240
Klaus Glasmacher, G. Zimmermann
Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard cell block layout is used to demonstrate a new strategy. Instead of generating the layouts of blocks in the same floorplan independently, layout proceeds in parallel and constraints like pin positions, shape and position of the blocks in the floorplan are exchanged dynamically. This method results in excellent adjustment of pin positions between cells and reduction of channel widths. Independent of the cell synthesis strategy is cell assembly, viewed as a topological compaction problem to refine the floorplans. A genetic algorithm is shown to solve this problem. Initial experimental results show the advantages of the new strategies.<>
{"title":"Chip assembly in the PLAYOUT VLSI design system","authors":"Klaus Glasmacher, G. Zimmermann","doi":"10.1109/EURDAC.1992.246240","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246240","url":null,"abstract":"Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard cell block layout is used to demonstrate a new strategy. Instead of generating the layouts of blocks in the same floorplan independently, layout proceeds in parallel and constraints like pin positions, shape and position of the blocks in the floorplan are exchanged dynamically. This method results in excellent adjustment of pin positions between cells and reduction of channel widths. Independent of the cell synthesis strategy is cell assembly, viewed as a topological compaction problem to refine the floorplans. A genetic algorithm is shown to solve this problem. Initial experimental results show the advantages of the new strategies.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123672474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246258
M. Mutz
The author presents basic concepts of defining semantics of the hardware description language VIOLA based on higher-order logic (HOL). The verification procedures of the hardware verification system VERENA are based on transformations of VIOLA terms. The correctness of these transformation steps can be formally verified based on the HOL semantics of the related VIOLA terms. As a mechanical tool, the HOL prove assistant is used. Basic concepts of a special verification system for the formal verification of digital circuits are presented. HOL serves as the formalism to define the underlying theory.<>
{"title":"Verification of digital circuits based on formal semantics of a hardware description language","authors":"M. Mutz","doi":"10.1109/EURDAC.1992.246258","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246258","url":null,"abstract":"The author presents basic concepts of defining semantics of the hardware description language VIOLA based on higher-order logic (HOL). The verification procedures of the hardware verification system VERENA are based on transformations of VIOLA terms. The correctness of these transformation steps can be formally verified based on the HOL semantics of the related VIOLA terms. As a mechanical tool, the HOL prove assistant is used. Basic concepts of a special verification system for the formal verification of digital circuits are presented. HOL serves as the formalism to define the underlying theory.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115559038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246230
J. Lienig, K. Thulasiraman, M. Swamy
Routing algorithms for multi-chip modules are presented. Two routing strategies, a channel routing and a grid-based routing, are discussed. The channel routing enables the designer to examine an effective routing during the placement phase. The grid-based routing calculates the net ordering with a new cost function and includes an effective rip-up and reroute procedure. The routing results of three different multichip modules are presented. Experimental results show that there is no direct correlation between the routing results of the channel algorithm and the grid-based one. It is concluded that channel routing is preferable only if the placement structure enables the generation of regular channels. In all other cases the grid-based algorithm is more effective using the channel routing just as a fast placement estimation.<>
{"title":"Routing algorithms for multi-chip modules","authors":"J. Lienig, K. Thulasiraman, M. Swamy","doi":"10.1109/EURDAC.1992.246230","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246230","url":null,"abstract":"Routing algorithms for multi-chip modules are presented. Two routing strategies, a channel routing and a grid-based routing, are discussed. The channel routing enables the designer to examine an effective routing during the placement phase. The grid-based routing calculates the net ordering with a new cost function and includes an effective rip-up and reroute procedure. The routing results of three different multichip modules are presented. Experimental results show that there is no direct correlation between the routing results of the channel algorithm and the grid-based one. It is concluded that channel routing is preferable only if the placement structure enables the generation of regular channels. In all other cases the grid-based algorithm is more effective using the channel routing just as a fast placement estimation.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125579059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246188
Djamel Boussebha, N. Giambiasi, J. Magnier
An approach for verifying the temporal scheduling of behavioral models of VHSIC hardware description language (VHDL) is presented. The aim is to verify that the control flow of a behavioral description satisfies its behavioral specifications described in a formalism based on reified temporal logics, and on a notion of physical activity. From this formalism, a verification procedure is established which starts by extracting the temporal subbehaviors from given VHDL descriptions and then gives them to the temporal demonstrator to prove whether they respect the behavioral specifications.<>
{"title":"Temporal verification of behavioral descriptions in VHDL","authors":"Djamel Boussebha, N. Giambiasi, J. Magnier","doi":"10.1109/EURDAC.1992.246188","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246188","url":null,"abstract":"An approach for verifying the temporal scheduling of behavioral models of VHSIC hardware description language (VHDL) is presented. The aim is to verify that the control flow of a behavioral description satisfies its behavioral specifications described in a formalism based on reified temporal logics, and on a notion of physical activity. From this formalism, a verification procedure is established which starts by extracting the temporal subbehaviors from given VHDL descriptions and then gives them to the temporal demonstrator to prove whether they respect the behavioral specifications.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131420737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246235
M. Kraak, R. Otten
The authors describe how the forward chaining mechanism of an expert system's inference engine is employed to achieve automated cost optimization in designing testable circuits. The characteristics of forward chaining are used to explore the set of applicable testability strategies. This exploration is preceded by a testability analysis, using a set of testability rules with the emphasis on maximization of fault coverage. The analysis locates the places in the design that are not optimally accessible, taking into account the characteristics of the concerning parts, such as function and design style. A testability synthesis is accomplished by the forward chaining inference engine. A conflict set is compiled, containing rules which relate to testability strategies that will relax the violations of the analysis rules. The forward chaining mechanism in combination with the structural testability analysis directly drives the testability strategy that makes the best use of the available circuit resources.<>
{"title":"Tackling cost optimization in testable design by forward inferencing","authors":"M. Kraak, R. Otten","doi":"10.1109/EURDAC.1992.246235","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246235","url":null,"abstract":"The authors describe how the forward chaining mechanism of an expert system's inference engine is employed to achieve automated cost optimization in designing testable circuits. The characteristics of forward chaining are used to explore the set of applicable testability strategies. This exploration is preceded by a testability analysis, using a set of testability rules with the emphasis on maximization of fault coverage. The analysis locates the places in the design that are not optimally accessible, taking into account the characteristics of the concerning parts, such as function and design style. A testability synthesis is accomplished by the forward chaining inference engine. A conflict set is compiled, containing rules which relate to testability strategies that will relax the violations of the analysis rules. The forward chaining mechanism in combination with the structural testability analysis directly drives the testability strategy that makes the best use of the available circuit resources.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114559621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：