Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246201
Sungho Kang, S. Szygenda
When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available.<>
{"title":"New design error modeling and metrics for design validation","authors":"Sungho Kang, S. Szygenda","doi":"10.1109/EURDAC.1992.246201","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246201","url":null,"abstract":"When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"91 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246241
Thomas Pförtner, S. Kiefl, R. Dachauer
The authors present a technique of employing pin assignment to improve the physical design of printed circuit boards. The technique is based on all pins of ASICs, and reduces wire lengths and via count. Design time is reduced by automation and a top-down design procedure. An algorithm for the pin assignment problem is presented, and the combination of pin assignment with global routing is described.<>
{"title":"Embedded pin assignment for top down system design","authors":"Thomas Pförtner, S. Kiefl, R. Dachauer","doi":"10.1109/EURDAC.1992.246241","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246241","url":null,"abstract":"The authors present a technique of employing pin assignment to improve the physical design of printed circuit boards. The technique is based on all pins of ASICs, and reduces wire lengths and via count. Design time is reduced by automation and a top-down design procedure. An algorithm for the pin assignment problem is presented, and the combination of pin assignment with global routing is described.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114099237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246339
A. Zamfirescu, C. Ussery
The authors explore the feasibility of using VHSIC hardware description language (VHDL) to model systems utilizing fuzzy logic. Emphasis is placed on the representation and analysis of the behavior of collections of interacting objects, each of which is characterized by fuzzy if-then rules. The feasibility and desirability of using VHDL to model such systems is examined, and an example is used to test the ideas developed. A discussion of the importance and future trends in modeling fuzzy logic using hardware description languages (HDLs), and VHDL in particular, is provided.<>
{"title":"VHDL and fuzzy logic if-then rules","authors":"A. Zamfirescu, C. Ussery","doi":"10.1109/EURDAC.1992.246339","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246339","url":null,"abstract":"The authors explore the feasibility of using VHSIC hardware description language (VHDL) to model systems utilizing fuzzy logic. Emphasis is placed on the representation and analysis of the behavior of collections of interacting objects, each of which is characterized by fuzzy if-then rules. The feasibility and desirability of using VHDL to model such systems is examined, and an example is used to test the ideas developed. A discussion of the importance and future trends in modeling fuzzy logic using hardware description languages (HDLs), and VHDL in particular, is provided.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131956284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246248
N. Azémard, V. Bonzom, D. Auvergne
Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given.<>
{"title":"P.Size: a sizing aid for optimized designs","authors":"N. Azémard, V. Bonzom, D. Auvergne","doi":"10.1109/EURDAC.1992.246248","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246248","url":null,"abstract":"Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128503763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246318
W. Mao, M. Ciletti
A quantitative measure of robustness is introduced and used to evaluate the quality of a set of test pattern pairs when multiple delay faults are present in the circuit under test. It is shown that robust test patterns discussed in many previous papers are actually special cases of the robustness measure. The measure can be used to guide the selection of test pairs for delay fault testing, and thereby improve the quality of the set of test pairs used to detect delay faults.<>
{"title":"A quantitative measure of robustness for delay fault testing","authors":"W. Mao, M. Ciletti","doi":"10.1109/EURDAC.1992.246318","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246318","url":null,"abstract":"A quantitative measure of robustness is introduced and used to evaluate the quality of a set of test pattern pairs when multiple delay faults are present in the circuit under test. It is shown that robust test patterns discussed in many previous papers are actually special cases of the robustness measure. The measure can be used to guide the selection of test pairs for delay fault testing, and thereby improve the quality of the set of test pairs used to detect delay faults.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134123883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246322
M. Brielmann, E. Kupitz
An open, extensible, administrative data schema that is based on electronic design interchange format (EDIF) is presented. The schema closely reflects the hardware design process. Thus, it enables the realization of central design management services. The use of a common schema implemented with the help of an object management system allows the integrated tools to share the data covered by this schema during runtime. Hence, online consistency management is supported.<>
{"title":"Representing the hardware design process by a common data schema","authors":"M. Brielmann, E. Kupitz","doi":"10.1109/EURDAC.1992.246322","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246322","url":null,"abstract":"An open, extensible, administrative data schema that is based on electronic design interchange format (EDIF) is presented. The schema closely reflects the hardware design process. Thus, it enables the realization of central design management services. The use of a common schema implemented with the help of an object management system allows the integrated tools to share the data covered by this schema during runtime. Hence, online consistency management is supported.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246338
B. Lutter, W. Glunz, F. Rammig
The authors present the use of VHSIC hardware description language (VHDL) for the simulation of Specification and Description Language (SDL) specification. SDL is a standardized graphical specification and description language. It is widely used for specifications of software systems that are based on message exchange, e.g., telecommunication systems. The approach presented allows for simulation of the logical correctness of the specification, as well as some kinds of performance simulation. A third application of the approach is the joint simulation of hardware and software. The translation of SDL into VHDL allows for functional, performance, and joint hardware/software simulation of systems specified with SDL.<>
{"title":"Using VHDL for simulation of SDL specifications","authors":"B. Lutter, W. Glunz, F. Rammig","doi":"10.1109/EURDAC.1992.246338","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246338","url":null,"abstract":"The authors present the use of VHSIC hardware description language (VHDL) for the simulation of Specification and Description Language (SDL) specification. SDL is a standardized graphical specification and description language. It is widely used for specifications of software systems that are based on message exchange, e.g., telecommunication systems. The approach presented allows for simulation of the logical correctness of the specification, as well as some kinds of performance simulation. A third application of the approach is the joint simulation of hardware and software. The translation of SDL into VHDL allows for functional, performance, and joint hardware/software simulation of systems specified with SDL.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125325083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246227
G. Cabodi, P. Camurati, Fulvio Corno, P. Prinetto, M. Reorda
The authors present a technique for assessing the diagnostic power of an existing detection-oriented test pattern by means of diagnostic fault simulation and a procedure to improve it. The procedure successfully exploits enhanced symbolic finite state machine (FSM) equivalence proof algorithms. In order to resort to product machine traversal only when needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to their equivalence class, this method may be used to build a complete and exact diagnostic tree. Experimental results support the claim that the diagnosis of real-world synchronous sequential circuits has become feasible for the first time.<>
{"title":"Cross-fertilizing FSM verification techniques and sequential diagnosis","authors":"G. Cabodi, P. Camurati, Fulvio Corno, P. Prinetto, M. Reorda","doi":"10.1109/EURDAC.1992.246227","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246227","url":null,"abstract":"The authors present a technique for assessing the diagnostic power of an existing detection-oriented test pattern by means of diagnostic fault simulation and a procedure to improve it. The procedure successfully exploits enhanced symbolic finite state machine (FSM) equivalence proof algorithms. In order to resort to product machine traversal only when needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to their equivalence class, this method may be used to build a complete and exact diagnostic tree. Experimental results support the claim that the diagnosis of real-world synchronous sequential circuits has become feasible for the first time.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130499280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246254
Shen Lin, E. Kuh
The authors present a new approach for transient simulation of lossy coupled transmission lines terminated in arbitrary nonlinear elements. The approach is based on convolution simulation. By making use of the Pade approximation of the modal functions, the impulse responses of the multiconductor system are determined. A recursive convolution formulations is derived for the impulse responses. The stepwise equivalent conductance integration technique is employed: therefore, no Newton-Raphson iteration is needed for the implicit integration of the circuit. The approach can handle general coupling situations.<>
{"title":"Transient simulation of lossy coupled transmission lines","authors":"Shen Lin, E. Kuh","doi":"10.1109/EURDAC.1992.246254","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246254","url":null,"abstract":"The authors present a new approach for transient simulation of lossy coupled transmission lines terminated in arbitrary nonlinear elements. The approach is based on convolution simulation. By making use of the Pade approximation of the modal functions, the impulse responses of the multiconductor system are determined. A recursive convolution formulations is derived for the impulse responses. The stepwise equivalent conductance integration technique is employed: therefore, no Newton-Raphson iteration is needed for the implicit integration of the circuit. The approach can handle general coupling situations.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127846016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246255
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Y. Lin
The interconnection synthesis problem in microarchitecture-level designs is addressed. With emphasis on the speed of data movement operations, algorithms are proposed that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. Two types of problems are considered: resource-constrained binding and performance-constrained binding. The integer linear programming (ILP) formulations are derived to optimally solve these problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Experimental results indicate that the proposed algorithms are very effective.<>
{"title":"Performance-driven interconnection optimization for microarchitecture synthesis","authors":"Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Y. Lin","doi":"10.1109/EURDAC.1992.246255","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246255","url":null,"abstract":"The interconnection synthesis problem in microarchitecture-level designs is addressed. With emphasis on the speed of data movement operations, algorithms are proposed that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. Two types of problems are considered: resource-constrained binding and performance-constrained binding. The integer linear programming (ILP) formulations are derived to optimally solve these problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Experimental results indicate that the proposed algorithms are very effective.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"92 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120872576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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