Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246225
Uwe Gläser, H. Vierhaus
Automatic test pattern generation in CMOS circuits from gate-level net lists is efficient, but has shortcomings with respect to fault coverage in complex and irregular CMOS gates and networks. An approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. The authors describe the gate level part of a tool for dynamically coupled gate-level and switch-level test generation. Acceptable performance and high fault coverage for non-trivial transistor networks are combined. Patterns generated in this way are inherently capable of detecting interrupt types of faults and transition faults. In combination with local overcurrent detectors, stuck-on and bridging faults can be identified.<>
{"title":"MILEF: an efficient approach to mixed level automatic test pattern generation","authors":"Uwe Gläser, H. Vierhaus","doi":"10.1109/EURDAC.1992.246225","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246225","url":null,"abstract":"Automatic test pattern generation in CMOS circuits from gate-level net lists is efficient, but has shortcomings with respect to fault coverage in complex and irregular CMOS gates and networks. An approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. The authors describe the gate level part of a tool for dynamically coupled gate-level and switch-level test generation. Acceptable performance and high fault coverage for non-trivial transistor networks are combined. Patterns generated in this way are inherently capable of detecting interrupt types of faults and transition faults. In combination with local overcurrent detectors, stuck-on and bridging faults can be identified.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"2674 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246324
L. Opalski, M. Styblinski
A new system called GOSSIP (generic optimization system for statistical improvement of performance) is described. GOSSIP can be considered as a new framework for optimal circuit design. It has several useful features, such as flexibility of combining various solution methods, scaling algorithms, circuit analyzers, etc. Two important design methodologies implemented in GOSSIP are described, based on a generalized least squares approach combined with designer aspiration levels and a generalized (in a fuzzy set sense) statistical design centering approach. A design example for a VLSI CMOS building block is given.<>
{"title":"GOSSIP-a generic system for statistical circuit design","authors":"L. Opalski, M. Styblinski","doi":"10.1109/EURDAC.1992.246324","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246324","url":null,"abstract":"A new system called GOSSIP (generic optimization system for statistical improvement of performance) is described. GOSSIP can be considered as a new framework for optimal circuit design. It has several useful features, such as flexibility of combining various solution methods, scaling algorithms, circuit analyzers, etc. Two important design methodologies implemented in GOSSIP are described, based on a generalized least squares approach combined with designer aspiration levels and a generalized (in a fuzzy set sense) statistical design centering approach. A design example for a VLSI CMOS building block is given.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246234
M. Bombana, G. Buonanno, P. Cavalloro, D. Sciuto, G. Zaza
The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules.<>
{"title":"A multilevel testability assistant for VLSI design","authors":"M. Bombana, G. Buonanno, P. Cavalloro, D. Sciuto, G. Zaza","doi":"10.1109/EURDAC.1992.246234","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246234","url":null,"abstract":"The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116353107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246232
T. Luba, K. Górski, L. Wronski
An effective method for the synthesis of address modifiers in sequential circuits is described. The method, based on serial decomposition, substantially reduces the address modifier circuit complexity for a given microprogram memory size. It can be used effectively for PMS based designs and for full custom designs. The method was implemented in C++ on a PC. It was tested on standard finite state machine (FSM) benchmarks. Results indicate that for a wide range of cases the method gives a substantial (more than 50%) reduction of required ROM capacity, which may result in a saving of the silicon area in the actual full custom implementation.<>
{"title":"ROM-based finite state machines with PLA address modifiers","authors":"T. Luba, K. Górski, L. Wronski","doi":"10.1109/EURDAC.1992.246232","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246232","url":null,"abstract":"An effective method for the synthesis of address modifiers in sequential circuits is described. The method, based on serial decomposition, substantially reduces the address modifier circuit complexity for a given microprogram memory size. It can be used effectively for PMS based designs and for full custom designs. The method was implemented in C++ on a PC. It was tested on standard finite state machine (FSM) benchmarks. Results indicate that for a wide range of cases the method gives a substantial (more than 50%) reduction of required ROM capacity, which may result in a saving of the silicon area in the actual full custom implementation.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123686782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246220
T. Koide, S. Wakabayashi, N. Yoshida
The authors present a linear time optimal algorithm to determine positions of the pins of nets on the top and the bottom sides of a channel, which is partitioned into several intervals. The pins are permutable within their associated intervals. The proposed algorithm is optimal in the sense that it can minimize both the density and the total wire length of the channel. Experimental results show that sufficient reduction of the channel density and the total wire length is, in fact, obtained by the use of the algorithm.<>
{"title":"An optimal channel pin assignment with multiple intervals for building block layout","authors":"T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/EURDAC.1992.246220","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246220","url":null,"abstract":"The authors present a linear time optimal algorithm to determine positions of the pins of nets on the top and the bottom sides of a channel, which is partitioned into several intervals. The pins are permutable within their associated intervals. The proposed algorithm is optimal in the sense that it can minimize both the density and the total wire length of the channel. Experimental results show that sufficient reduction of the channel density and the total wire length is, in fact, obtained by the use of the algorithm.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128268399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246269
Ronald B. Stewart, Véronique Anjubault, P. Garcin, J. Benkoski
Digital MOS transistor designs are imported into an environment of cell-based tools by division of the design into gate-level components followed by the automatic generation of their logical and timing views. Symbolic switch-level analysis divides the design into channel-connected components and provides estimates of their logical behavior. Electrical simulation verifies or corrects the logical model and yields a timing view.<>
{"title":"Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation","authors":"Ronald B. Stewart, Véronique Anjubault, P. Garcin, J. Benkoski","doi":"10.1109/EURDAC.1992.246269","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246269","url":null,"abstract":"Digital MOS transistor designs are imported into an environment of cell-based tools by division of the design into gate-level components followed by the automatic generation of their logical and timing views. Symbolic switch-level analysis divides the design into channel-connected components and provides estimates of their logical behavior. Electrical simulation verifies or corrects the logical model and yields a timing view.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129077794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246233
C. Shi, J. Brzozowski
A fast heuristic algorithm called ENCORE is proposed for the dichotomy-based constrained encoding problem. Its implementation has been tested on MCNC synchronous sequential logic benchmarks. For the case of complete encoding, ENCORE generates the same or shorter encoding lengths than the programs KISS, NOVA and DIET, for most of the benchmarks, and uses much less CPU time. For bounded-length encoding, ENCORE produces better overall quality than both random encoding and NOVA. ENCORE has also been applied to state assignment problems for asynchronous machines; it consistently obtains optimal or near-optimal results for a variety of examples found in the literature.<>
{"title":"Efficient constrained encoding for VLSI sequential logic synthesis","authors":"C. Shi, J. Brzozowski","doi":"10.1109/EURDAC.1992.246233","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246233","url":null,"abstract":"A fast heuristic algorithm called ENCORE is proposed for the dichotomy-based constrained encoding problem. Its implementation has been tested on MCNC synchronous sequential logic benchmarks. For the case of complete encoding, ENCORE generates the same or shorter encoding lengths than the programs KISS, NOVA and DIET, for most of the benchmarks, and uses much less CPU time. For bounded-length encoding, ENCORE produces better overall quality than both random encoding and NOVA. ENCORE has also been applied to state assignment problems for asynchronous machines; it consistently obtains optimal or near-optimal results for a variety of examples found in the literature.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130977898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246330
R. Davies
The author examines the technology shifts that will drive the electronic design automation (EDA) tools needed for right-first-time integrated system design. The major issues facing the design community and possible ways to improve productivity and quality are considered.<>
{"title":"Electronic systems design-tools and methodology to meet the productivity change","authors":"R. Davies","doi":"10.1109/EURDAC.1992.246330","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246330","url":null,"abstract":"The author examines the technology shifts that will drive the electronic design automation (EDA) tools needed for right-first-time integrated system design. The major issues facing the design community and possible ways to improve productivity and quality are considered.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246193
W. Ecker
Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal verification methods.<>
{"title":"Towards a common RT-level subset of VHDL","authors":"W. Ecker","doi":"10.1109/EURDAC.1992.246193","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246193","url":null,"abstract":"Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal verification methods.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246333
P. Eles, K. Kuchcinski, Zebo Peng, M. Minea
An approach to the use of VHDL (VHSIC hardware description language) as an input specification to the CAMAD high-level synthesis system is presented. A synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the interal design representation of CAMAD is described. CAMAD can then be synthesized into register-transfer level design. Since CAMAD supports the design of hardware with concurrency and asynchrony, the VHDL subset includes the concurrent features of the language. Conclusions concerning how to deal with signals, wait statements, structured data, and subprograms are presented.<>
{"title":"Compiling VHDL into a high-level synthesis design representation","authors":"P. Eles, K. Kuchcinski, Zebo Peng, M. Minea","doi":"10.1109/EURDAC.1992.246333","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246333","url":null,"abstract":"An approach to the use of VHDL (VHSIC hardware description language) as an input specification to the CAMAD high-level synthesis system is presented. A synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the interal design representation of CAMAD is described. CAMAD can then be synthesized into register-transfer level design. Since CAMAD supports the design of hardware with concurrency and asynchrony, the VHDL subset includes the concurrent features of the language. Conclusions concerning how to deal with signals, wait statements, structured data, and subprograms are presented.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126089412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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