Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246194
A. Debreil, P. Oddo
VHSIC hardware description language (VHDL) is a very rich and flexible language, which offers large possibilities in the simulation domain. The current state of the art of the formal proof technique does not enable handling all these possibilities. It applies only to synchronous descriptions. The author proposes definitions of the main object semantics to be used in a synchronous description. The resulting VHDL guidelines are described. These make up the bases of a VHDL subset suitable for formal proof and also for synthesis tools.<>
{"title":"Synchronous design in VHDL","authors":"A. Debreil, P. Oddo","doi":"10.1109/EURDAC.1992.246194","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246194","url":null,"abstract":"VHSIC hardware description language (VHDL) is a very rich and flexible language, which offers large possibilities in the simulation domain. The current state of the art of the formal proof technique does not enable handling all these possibilities. It applies only to synchronous descriptions. The author proposes definitions of the main object semantics to be used in a synchronous description. The resulting VHDL guidelines are described. These make up the bases of a VHDL subset suitable for formal proof and also for synthesis tools.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115503782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246267
Henning Spruth, G. Sigl
The authors present parallel algorithms for solving the final placement problem of rectangular modules assuming predefined neighborhood relations, between the modules to be placed. By enumerating all arrangements (i.e. slicing structures) of local module subsets, optimum solutions are obtained. They are combined in a global evaluation step such that the local solutions fit well into the global arrangement. Increased size of the enumerated local subproblems leads to placements that are closer to a global optimum. The resulting higher computational demands can be met by using parallel computers that provide huge amounts of computing power and distributed memory. New algorithms are proposed for the enumeration on message-passing parallel computers. Experimental results show that significant speedups as well as better results can be achieved.<>
{"title":"Parallel algorithms for slicing based final placement","authors":"Henning Spruth, G. Sigl","doi":"10.1109/EURDAC.1992.246267","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246267","url":null,"abstract":"The authors present parallel algorithms for solving the final placement problem of rectangular modules assuming predefined neighborhood relations, between the modules to be placed. By enumerating all arrangements (i.e. slicing structures) of local module subsets, optimum solutions are obtained. They are combined in a global evaluation step such that the local solutions fit well into the global arrangement. Increased size of the enumerated local subproblems leads to placements that are closer to a global optimum. The resulting higher computational demands can be met by using parallel computers that provide huge amounts of computing power and distributed memory. New algorithms are proposed for the enumeration on message-passing parallel computers. Experimental results show that significant speedups as well as better results can be achieved.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126800313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246239
Kuang-Chien Chen, J. Cong
Field programmable gate array (FPGA) is an important VLSI technology. Many algorithms have been proposed for the synthesis of FPGAs, but most of them concern issues in technology-mapping. The authors present a new logic minimization algorithm MR (maximal reduction) for the minimization of FPGA networks using lookup-tables. Information is obtained on how to remove the lookup tables by using network resynthesis techniques. Order-independent and global optimal results are obtained by formulating the lookup-table minimization problem as a maximum independent set problem. Experimental results show that MR can significantly improve the designs obtained by existing FPGA synthesis algorithms.<>
{"title":"Maximal reduction of lookup-table based FPGAs","authors":"Kuang-Chien Chen, J. Cong","doi":"10.1109/EURDAC.1992.246239","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246239","url":null,"abstract":"Field programmable gate array (FPGA) is an important VLSI technology. Many algorithms have been proposed for the synthesis of FPGAs, but most of them concern issues in technology-mapping. The authors present a new logic minimization algorithm MR (maximal reduction) for the minimization of FPGA networks using lookup-tables. Information is obtained on how to remove the lookup tables by using network resynthesis techniques. Order-independent and global optimal results are obtained by formulating the lookup-table minimization problem as a maximum independent set problem. Experimental results show that MR can significantly improve the designs obtained by existing FPGA synthesis algorithms.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125938000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246202
S. Kuo
The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exist between the specification and the implementation. This technique can determine the region containing the error. It has very high resolution and reduces the debugging time by the designers. Extensive experimental results were obtained to demonstrate the effectiveness of the new approach.<>
{"title":"Locating logic design errors via test generation and don't-care propagation","authors":"S. Kuo","doi":"10.1109/EURDAC.1992.246202","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246202","url":null,"abstract":"The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exist between the specification and the implementation. This technique can determine the region containing the error. It has very high resolution and reduces the debugging time by the designers. Extensive experimental results were obtained to demonstrate the effectiveness of the new approach.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"11 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126101275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246250
E. Felt, E. Charbon, E. Malavasi, A. Sangiovanni-Vincentelli
An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.<>
{"title":"An efficient methodology for symbolic compaction of analog ICs with multiple symmetry constraints","authors":"E. Felt, E. Charbon, E. Malavasi, A. Sangiovanni-Vincentelli","doi":"10.1109/EURDAC.1992.246250","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246250","url":null,"abstract":"An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246316
C. Gloster, F. Brglez
The authors re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. A dynamic scan test generation algorithm, DYNASTEE, is introduced. It reduces test sequence length when compared to existing static test generation algorithms for scan architectures. It is shown that test sequence length can be minimized further by re-ordering the scan chain.<>
{"title":"Cellular scan test generation for sequential circuits","authors":"C. Gloster, F. Brglez","doi":"10.1109/EURDAC.1992.246316","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246316","url":null,"abstract":"The authors re-examine the concept of test machine embedding and present a new test machine architecture: cellular scan. Unlike the traditional scan machine architecture, the cellular scan machine requires no scan-out pin. A dynamic scan test generation algorithm, DYNASTEE, is introduced. It reduces test sequence length when compared to existing static test generation algorithms for scan architectures. It is shown that test sequence length can be minimized further by re-ordering the scan chain.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246253
E. Bolender, H. Lipp
The authors describe a new method of timing verification that searches the longest sensitizable path of a combinationorial network. The algorithm is exact in the sense that an exhaustive simulation would produce the same result. The concept of robustness in the algorithm is included. The extension of the theory for edge dependent delays has been completed.<>
{"title":"The exact solution of timing verification","authors":"E. Bolender, H. Lipp","doi":"10.1109/EURDAC.1992.246253","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246253","url":null,"abstract":"The authors describe a new method of timing verification that searches the longest sensitizable path of a combinationorial network. The algorithm is exact in the sense that an exhaustive simulation would produce the same result. The concept of robustness in the algorithm is included. The extension of the theory for edge dependent delays has been completed.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125208194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246209
W. Rissiek, W. John
A new scheduling algorithm for waveform relaxation is presented. The algorithm is based on information about the circuit structure and the dynamic behavior of the circuit. As the new scheduling algorithm does not depend on the circuit technology, bipolar circuits can also be simulated using the waveform relaxation method. The examples presented show a speedup factor of two compared to other schedules. The reliability of the waveform relaxation method for the simulation of bipolar circuits is improved, too. In this context the dynamic overlapping algorithm results in a robust convergence, especially for bipolar circuits.<>
{"title":"A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation","authors":"W. Rissiek, W. John","doi":"10.1109/EURDAC.1992.246209","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246209","url":null,"abstract":"A new scheduling algorithm for waveform relaxation is presented. The algorithm is based on information about the circuit structure and the dynamic behavior of the circuit. As the new scheduling algorithm does not depend on the circuit technology, bipolar circuits can also be simulated using the waveform relaxation method. The examples presented show a speedup factor of two compared to other schedules. The reliability of the waveform relaxation method for the simulation of bipolar circuits is improved, too. In this context the dynamic overlapping algorithm results in a robust convergence, especially for bipolar circuits.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246196
J. Rouillard
VHSIC hardware description language (VHDL) 1076 is an IEEE standard which is undergoing a restandardization process. The restandardization process has gone through several phases. The first was the collection and analysis of users' requirements. It is shown how the decision process works, both at an administrative and a technical level. The origins of the requirements and the classification of the analyzed requirements are shown. The question of analog requirements is explained. A paradigmatic controversial example is detailed (global variables), and a list of available documents is given.<>
{"title":"Analysis of user requirements","authors":"J. Rouillard","doi":"10.1109/EURDAC.1992.246196","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246196","url":null,"abstract":"VHSIC hardware description language (VHDL) 1076 is an IEEE standard which is undergoing a restandardization process. The restandardization process has gone through several phases. The first was the collection and analysis of users' requirements. It is shown how the decision process works, both at an administrative and a technical level. The origins of the requirements and the classification of the analyzed requirements are shown. The question of analog requirements is explained. A paradigmatic controversial example is detailed (global variables), and a list of available documents is given.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115080185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246325
Min Huang, M. Styblinski
A generic software system called GOSSIPDR (generic optimization system for statistical improvement of performance) to perform DR (drift reliability) analysis and optimization is presented. This system was developed based on new DR analysis and optimization methodologies. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations due to hot electron effects are considered.<>
提出了一种用于漂移可靠性分析和优化的通用软件系统——gossip pdr (generic optimization system for statistical improvement of performance)。该系统是基于新的DR分析和优化方法开发的。介绍了几个有用的系统特性和功能。给出了在超大规模集成电路设计中的应用，其中考虑了热电子效应引起的退化。
{"title":"A generic software system for drift reliability optimization of VLSI circuits","authors":"Min Huang, M. Styblinski","doi":"10.1109/EURDAC.1992.246325","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246325","url":null,"abstract":"A generic software system called GOSSIPDR (generic optimization system for statistical improvement of performance) to perform DR (drift reliability) analysis and optimization is presented. This system was developed based on new DR analysis and optimization methodologies. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations due to hot electron effects are considered.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"620 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116456489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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