Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5630891
V. Pesonen, M. Gorev, P. Annus, Mart Min, P. Ellervee
Multi-channel data-acquisition devices are used often in biomedicine to measure properties of organs/tissues. A DSP-based solution for a multi-frequency measurement unit has been proposed and implemented. In this paper, extensions to the existing prototype data acquisition unit are discussed. The extensions were designed to allow to reduce the aliasing effect.
{"title":"Reconfigurable data acquisition unit for bioimpedance measurements","authors":"V. Pesonen, M. Gorev, P. Annus, Mart Min, P. Ellervee","doi":"10.1109/BEC.2010.5630891","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630891","url":null,"abstract":"Multi-channel data-acquisition devices are used often in biomedicine to measure properties of organs/tissues. A DSP-based solution for a multi-frequency measurement unit has been proposed and implemented. In this paper, extensions to the existing prototype data acquisition unit are discussed. The extensions were designed to allow to reduce the aliasing effect.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5631522
A. Kalanti, L. Aaltonen, M. Paavola, M. Kamarainen, M. Pulkkinen, K. Halonen
As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.
随着数字电路模块的复杂性不断增加，需要一个上电复位(POR)电路来将数字逻辑初始化到启动时的已知状态。本文描述了一个阈值对电源电压上升时间不敏感的POR。这是通过用恒流参考电路产生POR脉冲来实现的。此外，采用电流镜像来改善磁滞。设计的POR静态电流为3.1 μ a (VDD=3.6 V)，工作电源范围为3 V至3.6 V。电路面积为109.9µm × 106.65µm，芯片采用三孔0.35µm HVCMOS工艺实现。
{"title":"A power-on reset with accurate hysteresis","authors":"A. Kalanti, L. Aaltonen, M. Paavola, M. Kamarainen, M. Pulkkinen, K. Halonen","doi":"10.1109/BEC.2010.5631522","DOIUrl":"https://doi.org/10.1109/BEC.2010.5631522","url":null,"abstract":"As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130369372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5630284
J. Kroustek, S. Židek, D. Kolář, A. Meduna
More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.
{"title":"Exploitation of scattered context grammars to model VLIW instruction constraints","authors":"J. Kroustek, S. Židek, D. Kolář, A. Meduna","doi":"10.1109/BEC.2010.5630284","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630284","url":null,"abstract":"More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129859204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5630057
S. Strik, V. Strik
The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range −40∶125°C.
{"title":"High accuracy, low temperature coefficient bandgap voltage reference","authors":"S. Strik, V. Strik","doi":"10.1109/BEC.2010.5630057","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630057","url":null,"abstract":"The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range −40∶125°C.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5631842
U. Reinsalu, J. Raik, R. Ubar
The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.
{"title":"Register-transfer level deductive fault simulation using decision diagrams","authors":"U. Reinsalu, J. Raik, R. Ubar","doi":"10.1109/BEC.2010.5631842","DOIUrl":"https://doi.org/10.1109/BEC.2010.5631842","url":null,"abstract":"The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5630164
A. Talisainen, S. Kostin, D. Karai, I. Fridolin, R. Ubar
Objective: develop signal processing algorithm for the removal of disturbances not related to treatment course and compare with available clinical data.
目的:开发与疗程无关的信号处理算法，并与现有临床数据进行比较。
{"title":"On-line monitoring of dialysis adequacy using DiaSens optical sensor: Accurate Kt/V estimation by smoothing algorithms","authors":"A. Talisainen, S. Kostin, D. Karai, I. Fridolin, R. Ubar","doi":"10.1109/BEC.2010.5630164","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630164","url":null,"abstract":"Objective: develop signal processing algorithm for the removal of disturbances not related to treatment course and compare with available clinical data.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5630014
D. Wojciechowski, R. Strzelecki
The paper present the model based predictive controller for ripple free, high power active filter (APF) with LCL circuit. The system suppresses LCL resonance and provides control dynamics limited only by circuit parameters. The inverter of an active power filter requires a high PWM switching frequency, therefore high power application has to be realized by using several power modules operating in parallel. There are presented simulations and experimental results achieved for APF system of the rated power 1.2MVA with four 300 kVA power blocks operating in parallel.
{"title":"High power, zero ripples active filtering system with power modules operating in parallel","authors":"D. Wojciechowski, R. Strzelecki","doi":"10.1109/BEC.2010.5630014","DOIUrl":"https://doi.org/10.1109/BEC.2010.5630014","url":null,"abstract":"The paper present the model based predictive controller for ripple free, high power active filter (APF) with LCL circuit. The system suppresses LCL resonance and provides control dynamics limited only by circuit parameters. The inverter of an active power filter requires a high PWM switching frequency, therefore high power application has to be realized by using several power modules operating in parallel. There are presented simulations and experimental results achieved for APF system of the rated power 1.2MVA with four 300 kVA power blocks operating in parallel.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122383205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5629730
M. Talonen, J. Ryynanen
In this paper we describe initial steps that we have taken to create an open source machine processable ontology to store domain knowledge about the analog and mixed signal circuit and systems. It is seen that an openly available semantic knowledge base could be beneficial in distributing circuit and system domain knowledge. This knowledge could be used to leverage productivity of the early phase architectural exploration by having easier access to review implementation domain. Main design goals for the ontology has been interoperability issues and transparency and re-usability of the described data. This is guaranteed by using standard knowledge representation language with well defined semantics and by associating all of the data in the ontology to the corresponding reference by using annotations.
{"title":"Analog and mixed signal circuit and system ontology","authors":"M. Talonen, J. Ryynanen","doi":"10.1109/BEC.2010.5629730","DOIUrl":"https://doi.org/10.1109/BEC.2010.5629730","url":null,"abstract":"In this paper we describe initial steps that we have taken to create an open source machine processable ontology to store domain knowledge about the analog and mixed signal circuit and systems. It is seen that an openly available semantic knowledge base could be beneficial in distributing circuit and system domain knowledge. This knowledge could be used to leverage productivity of the early phase architectural exploration by having easier access to review implementation domain. Main design goals for the ontology has been interoperability issues and transparency and re-usability of the described data. This is guaranteed by using standard knowledge representation language with well defined semantics and by associating all of the data in the ontology to the corresponding reference by using annotations.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"479 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5629729
O. Vainio, E. Salminen, J. Takala
This paper presents how the course syllabus for digital and computer systems education at our department has been adapted to utilize the same FPGA-based hardware platform in many laboratory exercises. The reform has been carried out in order to streamline the learning towards core content instead of studying multiple complex design software and hardware environments. Each student is given a package including an FPGA board and related design tools. In addition to the course exercises, the students are encouraged to use it also for thesis projects and hobbies. In this paper, we describe the syllabus, the key courses, and the platform used in education of microelectronic systems. Examples of completed thesis works are given.
{"title":"Teaching digital systems using a unified FPGA platform","authors":"O. Vainio, E. Salminen, J. Takala","doi":"10.1109/BEC.2010.5629729","DOIUrl":"https://doi.org/10.1109/BEC.2010.5629729","url":null,"abstract":"This paper presents how the course syllabus for digital and computer systems education at our department has been adapted to utilize the same FPGA-based hardware platform in many laboratory exercises. The reform has been carried out in order to streamline the learning towards core content instead of studying multiple complex design software and hardware environments. Each student is given a package including an FPGA board and related design tools. In addition to the course exercises, the students are encouraged to use it also for thesis projects and hobbies. In this paper, we describe the syllabus, the key courses, and the platform used in education of microelectronic systems. Examples of completed thesis works are given.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117316856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-11DOI: 10.1109/BEC.2010.5629899
A. Kasemaa, T. Rang
The paper gives short overview of an efficient CMOS technology based current source realization and layout design. The current source output will be shortened square wave signal [1],[2] and [3]. The output current value can be selected from range 5 to 100µA. The current source layout design needs good matching, the geometry and temperature influence has been analyzed and the optimal geometrical structure will be suggested.
{"title":"Low power CMOS current source for shortened square wave signals","authors":"A. Kasemaa, T. Rang","doi":"10.1109/BEC.2010.5629899","DOIUrl":"https://doi.org/10.1109/BEC.2010.5629899","url":null,"abstract":"The paper gives short overview of an efficient CMOS technology based current source realization and layout design. The current source output will be shortened square wave signal [1],[2] and [3]. The output current value can be selected from range 5 to 100µA. The current source layout design needs good matching, the geometry and temperature influence has been analyzed and the optimal geometrical structure will be suggested.","PeriodicalId":228594,"journal":{"name":"2010 12th Biennial Baltic Electronics Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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