Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202245
R. Dharia, C.D. Johnson
Optimal control problems involve uncertain external disturbances w(t) and/or set-point/servo-commands y/sub c/(t). The authors consider a class of a linear-quadratic set-point problems with disturbances and use a reverse-time solution procedure introduced by Kalman to solve the absolute optimal control under the idealistic case that at each time t the future behaviors of y/sub c/(t) and w(t) are completely known a priori. An alternative optimal control is also developed using the optimal disturbance-utilizing control (DUC) theory in which future behaviors of (y/sub c/(t), w(t)) are not known but, rather, sparse-impulse driven state-models of y/sub c/(t) and w(t) are introduced. The general similarities and differences in the two optimal controls are discussed and specific versions of those controls are derived for a concrete example. Optimal DUC control is apparently the best of all rational physically realizable controls for the class of problems considered.<>
{"title":"On the theoretical sub-optimality of optimal disturbance-utilizing control laws","authors":"R. Dharia, C.D. Johnson","doi":"10.1109/SECON.1992.202245","DOIUrl":"https://doi.org/10.1109/SECON.1992.202245","url":null,"abstract":"Optimal control problems involve uncertain external disturbances w(t) and/or set-point/servo-commands y/sub c/(t). The authors consider a class of a linear-quadratic set-point problems with disturbances and use a reverse-time solution procedure introduced by Kalman to solve the absolute optimal control under the idealistic case that at each time t the future behaviors of y/sub c/(t) and w(t) are completely known a priori. An alternative optimal control is also developed using the optimal disturbance-utilizing control (DUC) theory in which future behaviors of (y/sub c/(t), w(t)) are not known but, rather, sparse-impulse driven state-models of y/sub c/(t) and w(t) are introduced. The general similarities and differences in the two optimal controls are discussed and specific versions of those controls are derived for a concrete example. Optimal DUC control is apparently the best of all rational physically realizable controls for the class of problems considered.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202425
C. Katsinis
A node in a switch architecture is examined. The node receives messages, stores and processes them locally, and transmits them to other nodes. Both message transmission and processing times depend on the message length, which is a random variable. The node is modeled as a queue with a single server where the interarrival and service times are related, and different cases are studied where this relation ranges from direct dependence to moderate correlation. Exponential and uniform probability density functions (pdf's) are examined, and the results are compared to the independent model. A relationship is developed for the system time pdf of a message, which is used to find the system time pdf and the system state probabilities. These quantities are directly related to buffer sizes and transmission delays within the architecture.<>
{"title":"The effect of related message transfer and process times on waiting times and buffer sizes in switch architectures","authors":"C. Katsinis","doi":"10.1109/SECON.1992.202425","DOIUrl":"https://doi.org/10.1109/SECON.1992.202425","url":null,"abstract":"A node in a switch architecture is examined. The node receives messages, stores and processes them locally, and transmits them to other nodes. Both message transmission and processing times depend on the message length, which is a random variable. The node is modeled as a queue with a single server where the interarrival and service times are related, and different cases are studied where this relation ranges from direct dependence to moderate correlation. Exponential and uniform probability density functions (pdf's) are examined, and the results are compared to the independent model. A relationship is developed for the system time pdf of a message, which is used to find the system time pdf and the system state probabilities. These quantities are directly related to buffer sizes and transmission delays within the architecture.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"562 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120877638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202365
H. Ma, Y. Liu
The authors present a testable design to test pattern sensitive faults efficiently for semiconductor random access memories to reduce test time and hence test cost. Testability was achieved by including additional hardware. The additional hardware is composed of a special mode counter, an error checker, a modified column decoder, and one extra control pinout. The functional test procedure proposed is of length 512 (1+n/sup 1/2/) read and write operations for an n cell memory, and covers stuck-at, transition, coupling, and nine-cell neighborhood pattern sensitive faults. This design has an estimated overhead of 5% chip area and one additional pinout.<>
{"title":"A testable design to test pattern sensitive faults efficiently for semiconductor RAM","authors":"H. Ma, Y. Liu","doi":"10.1109/SECON.1992.202365","DOIUrl":"https://doi.org/10.1109/SECON.1992.202365","url":null,"abstract":"The authors present a testable design to test pattern sensitive faults efficiently for semiconductor random access memories to reduce test time and hence test cost. Testability was achieved by including additional hardware. The additional hardware is composed of a special mode counter, an error checker, a modified column decoder, and one extra control pinout. The functional test procedure proposed is of length 512 (1+n/sup 1/2/) read and write operations for an n cell memory, and covers stuck-at, transition, coupling, and nine-cell neighborhood pattern sensitive faults. This design has an estimated overhead of 5% chip area and one additional pinout.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124367840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202394
T. Wang, J. Foster
Adaptive vector quantization (AVQ) is presented as a waveform coding system with applications to digital voice transmission. The AVQ coding algorithms were modeled and simulated on a computer. Simulation results of higher dimensions are presented. A 20 min digitized speech was used as the source. Both quantitative and subjective tests were performed to compare the reconstructed speech with the original waveform. The transmission rate chosen was 16 kb/s. The results showed high signal-to-noise-ratio (SNR) performance with relatively low coding complexity.<>
{"title":"High dimension adaptive vector quantization","authors":"T. Wang, J. Foster","doi":"10.1109/SECON.1992.202394","DOIUrl":"https://doi.org/10.1109/SECON.1992.202394","url":null,"abstract":"Adaptive vector quantization (AVQ) is presented as a waveform coding system with applications to digital voice transmission. The AVQ coding algorithms were modeled and simulated on a computer. Simulation results of higher dimensions are presented. A 20 min digitized speech was used as the source. Both quantitative and subjective tests were performed to compare the reconstructed speech with the original waveform. The transmission rate chosen was 16 kb/s. The results showed high signal-to-noise-ratio (SNR) performance with relatively low coding complexity.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124545434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202397
M. Maloof
A promising application of knowledge-based systems is that of prescribing the most appropriate analytical method for a given situation. The Analytical Method Recommendation System (AMRS) services an entire laboratory containing several analytical instruments. It assists the inexperienced analytical chemist and permits technicians to become more independent from managing chemists. AMRS presently exists as an early prototype. The author discusses the knowledge acquisition methodology and design issues. Brief descriptions of current system performance and future directions are included.<>
{"title":"AMRS: a prototype of an analytical method recommendation system","authors":"M. Maloof","doi":"10.1109/SECON.1992.202397","DOIUrl":"https://doi.org/10.1109/SECON.1992.202397","url":null,"abstract":"A promising application of knowledge-based systems is that of prescribing the most appropriate analytical method for a given situation. The Analytical Method Recommendation System (AMRS) services an entire laboratory containing several analytical instruments. It assists the inexperienced analytical chemist and permits technicians to become more independent from managing chemists. AMRS presently exists as an early prototype. The author discusses the knowledge acquisition methodology and design issues. Brief descriptions of current system performance and future directions are included.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124547465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202430
K. Walsh, H. Henderson, G. D. De Brabander
The design and development of a second-generation miniature piezoresistive micromachined accelerometer are presented. Bulk micromachining etching techniques were utilized in the fabrication of the single-crystalline silicon device. The sensor is essentially its own package, consisting of three carefully aligned
{"title":"A fully-packaged silicon micromachined piezoresistive accelerometer","authors":"K. Walsh, H. Henderson, G. D. De Brabander","doi":"10.1109/SECON.1992.202430","DOIUrl":"https://doi.org/10.1109/SECON.1992.202430","url":null,"abstract":"The design and development of a second-generation miniature piezoresistive micromachined accelerometer are presented. Bulk micromachining etching techniques were utilized in the fabrication of the single-crystalline silicon device. The sensor is essentially its own package, consisting of three carefully aligned","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202285
Abhishek Gupta, C. Mazumdar
The authors investigate methods to speed up the match phase of the execution of production systems. The Rete match algorithm is taken as the basis of the implementation. A partially shared Rete network is proposed for parallel implementation and a hierarchical two-level parallel architecture based on this network is outlined. The proposed architecture achieves significant speedup by reducing the dynamic scheduling overheads of fine-grained jobs in a multiprocessor implementation of the Rete network, while still taking advantage of the sharing of common computations in the network.<>
{"title":"PMM: a parallel architecture for production systems","authors":"Abhishek Gupta, C. Mazumdar","doi":"10.1109/SECON.1992.202285","DOIUrl":"https://doi.org/10.1109/SECON.1992.202285","url":null,"abstract":"The authors investigate methods to speed up the match phase of the execution of production systems. The Rete match algorithm is taken as the basis of the implementation. A partially shared Rete network is proposed for parallel implementation and a hierarchical two-level parallel architecture based on this network is outlined. The proposed architecture achieves significant speedup by reducing the dynamic scheduling overheads of fine-grained jobs in a multiprocessor implementation of the Rete network, while still taking advantage of the sharing of common computations in the network.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202277
J. Karaoguz, S. Ardalan, M. Steer, C. Chang
A simulation environment for the analysis and design of RF communication systems from the link level down to the nonlinear circuit level was developed. The integrated simulation environment supports block diagram representations, multirate sampling, and an interactive graphical user interface. It permits the incorporation of sophisticated user models of individual blocks, in a mixed time-domain and frequency-domain environment. The simulation of a multichannel mobile communication system is presented. Large-signal nonlinear distortion effects due to the RF receiver front end, such as harmonic distortion, intermodulation distortion, and spurious noise, were obtained using the integrated link-level and circuit-level simulation environment. Results of large-signal effects on adjacent channel interference and signal-to-noise ratio are also presented.<>
{"title":"An integrated simulation environment for design and analysis of mobile communication systems","authors":"J. Karaoguz, S. Ardalan, M. Steer, C. Chang","doi":"10.1109/SECON.1992.202277","DOIUrl":"https://doi.org/10.1109/SECON.1992.202277","url":null,"abstract":"A simulation environment for the analysis and design of RF communication systems from the link level down to the nonlinear circuit level was developed. The integrated simulation environment supports block diagram representations, multirate sampling, and an interactive graphical user interface. It permits the incorporation of sophisticated user models of individual blocks, in a mixed time-domain and frequency-domain environment. The simulation of a multichannel mobile communication system is presented. Large-signal nonlinear distortion effects due to the RF receiver front end, such as harmonic distortion, intermodulation distortion, and spurious noise, were obtained using the integrated link-level and circuit-level simulation environment. Results of large-signal effects on adjacent channel interference and signal-to-noise ratio are also presented.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115703262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202388
P. Waknis, G. Karsai, J. Sztipanovits
The authors have developed a graphical programming library for control and signal processing applications. The library covers a wide range starting from basic primitives such as simple arithmetic and Boolean functions to complicated units like generalized neural networks. The user gets access to these units in the form of icons. By making connections to and from these icons, a user generates different block diagrams, which are the programs in the graphical environment. The library is described from the user's point of view. Different features of the graphical programming environment and the library are discussed. The use of the library is illustrated with a simple graphical programming example. Some of the implementation details are discussed.<>
{"title":"A graphical programming environment for simulation of control and signal processing systems","authors":"P. Waknis, G. Karsai, J. Sztipanovits","doi":"10.1109/SECON.1992.202388","DOIUrl":"https://doi.org/10.1109/SECON.1992.202388","url":null,"abstract":"The authors have developed a graphical programming library for control and signal processing applications. The library covers a wide range starting from basic primitives such as simple arithmetic and Boolean functions to complicated units like generalized neural networks. The user gets access to these units in the form of icons. By making connections to and from these icons, a user generates different block diagrams, which are the programs in the graphical environment. The library is described from the user's point of view. Different features of the graphical programming environment and the library are discussed. The use of the library is illustrated with a simple graphical programming example. Some of the implementation details are discussed.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132635938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202252
D. J. Jackson, D.M. Whiteside, L. Wurtz
A number of important characteristics for a graph, which may represent a set of parallel application tasks or a parallel computer architecture, can be extracted by analyzing the Boolean matrix corresponding to the graph. The characteristic of concern is the determination of minimum path lengths for various classes of regularly structured graphs. All the example graphs vary in terms of connectivity and sparsity and provide a suitable testbed for the analysis of the various algorithms used in determining powers of the Boolean matrices. Improvements for these algorithms are introduced which exploit the Boolean nature of the matrices and the inherent bit-level parallelism available in any N-bit computer system. An algorithm is introduced which exploits this bit-level parallelism and a number of graphs were analyzed utilizing a high-performance IBM RS/6000 workstation to demonstrate the merits of the algorithm.<>
{"title":"Exploiting bit-level parallelism in Boolean matrix operations for graph analysis","authors":"D. J. Jackson, D.M. Whiteside, L. Wurtz","doi":"10.1109/SECON.1992.202252","DOIUrl":"https://doi.org/10.1109/SECON.1992.202252","url":null,"abstract":"A number of important characteristics for a graph, which may represent a set of parallel application tasks or a parallel computer architecture, can be extracted by analyzing the Boolean matrix corresponding to the graph. The characteristic of concern is the determination of minimum path lengths for various classes of regularly structured graphs. All the example graphs vary in terms of connectivity and sparsity and provide a suitable testbed for the analysis of the various algorithms used in determining powers of the Boolean matrices. Improvements for these algorithms are introduced which exploit the Boolean nature of the matrices and the inherent bit-level parallelism available in any N-bit computer system. An algorithm is introduced which exploits this bit-level parallelism and a number of graphs were analyzed utilizing a high-performance IBM RS/6000 workstation to demonstrate the merits of the algorithm.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130804937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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