At the third High-Level Synthesis Workshop held in January 1988 at Orcas Island, Washington, participants were asked to submit papers describing the application of their systems and algorithms to set of benchmarks. The authors briefly describe the benchmarks and use them as a foundation for outlining the major themes in the research work presented at the workshop. They conclude with a summary of the discussions held during the course of the workshop on the future development of the high-level synthesis benchmark suite.<>
{"title":"High-level synthesis: current status and future directions","authors":"G. Borriello, E. Detjens","doi":"10.1109/DAC.1988.14802","DOIUrl":"https://doi.org/10.1109/DAC.1988.14802","url":null,"abstract":"At the third High-Level Synthesis Workshop held in January 1988 at Orcas Island, Washington, participants were asked to submit papers describing the application of their systems and algorithms to set of benchmarks. The authors briefly describe the benchmarks and use them as a foundation for outlining the major themes in the research work presented at the workshop. They conclude with a summary of the discussions held during the course of the workshop on the future development of the high-level synthesis benchmark suite.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design automation in the component-parts industry from purchase inquiry to finished product delivered is described. The computerized process simulates human decision-makers, eliminates bottlenecks, and frees human decision-makers from routine work. Fuzzy set analysis is used in the early stages of a design process. Its language describes well the imprecise or blurred specifications at the initial phase of an engineering design. The mathematics of fuzzy-set analysis leads naturally to a process which is similar to heuristic selection for realizing the product selection and design specification program (PSDS) in the computerized process.<>
{"title":"Design automation for the component parts industry","authors":"Sheldon S. L. Chang","doi":"10.5555/285730.285836","DOIUrl":"https://doi.org/10.5555/285730.285836","url":null,"abstract":"Design automation in the component-parts industry from purchase inquiry to finished product delivered is described. The computerized process simulates human decision-makers, eliminates bottlenecks, and frees human decision-makers from routine work. Fuzzy set analysis is used in the early stages of a design process. Its language describes well the imprecise or blurred specifications at the initial phase of an engineering design. The mathematics of fuzzy-set analysis leads naturally to a process which is similar to heuristic selection for realizing the product selection and design specification program (PSDS) in the computerized process.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A connectivity verification program implemented in PROLOG is presented. The major advantage of this program, called VERCON, over existing approaches is that it always works, irrespective of circuit topology. VERCON's approach to connectivity verification is to extract all the different designer-specified subcircuits from the flat transistor description. Verification is achieved when the top-level object is extracted and there are no transistors which were not used to form the top-level object. Although VERCON is a research prototype, several valuable conclusions have been drawn that will aid the design of a connectivity verification program written in C.<>
{"title":"A PROLOG-based connectivity verification tool","authors":"A.C. Papaspyridis","doi":"10.1109/DAC.1988.14810","DOIUrl":"https://doi.org/10.1109/DAC.1988.14810","url":null,"abstract":"A connectivity verification program implemented in PROLOG is presented. The major advantage of this program, called VERCON, over existing approaches is that it always works, irrespective of circuit topology. VERCON's approach to connectivity verification is to extract all the different designer-specified subcircuits from the flat transistor description. Verification is achieved when the top-level object is extracted and there are no transistors which were not used to form the top-level object. Although VERCON is a research prototype, several valuable conclusions have been drawn that will aid the design of a connectivity verification program written in C.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134037805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Algorithms are described for calculating controllabilities and observabilities at the switch level, primitives being the MOS switches which conduct in a definite direction. The signal flow direction of each transistor can be found using some heuristic rules developed by N.P. Jouppi (1983). The calculation of controllabilities is then a matter of propagating the probabilities, modulated by the probability that each transistor is conducting, into internal nets of the circuit, starting from the primary inputs of the circuit. As the signals fan in or fan out, the usual probability combination rules are used to estimate the new controllability and observability. The procedures used for assigning directions to MOS switches are discussed. The algorithms are implemented in LTIME, a CMOS timing analyzer. The techniques are also applied to dynamic power dissipation analysis, of CMOS circuits and are used in predicting chip-level failure rates due to hot-electron effects.<>
{"title":"Switch level random pattern testability analysis","authors":"Mehmet A. Cirit","doi":"10.1109/DAC.1988.14821","DOIUrl":"https://doi.org/10.1109/DAC.1988.14821","url":null,"abstract":"Algorithms are described for calculating controllabilities and observabilities at the switch level, primitives being the MOS switches which conduct in a definite direction. The signal flow direction of each transistor can be found using some heuristic rules developed by N.P. Jouppi (1983). The calculation of controllabilities is then a matter of propagating the probabilities, modulated by the probability that each transistor is conducting, into internal nets of the circuit, starting from the primary inputs of the circuit. As the signals fan in or fan out, the usual probability combination rules are used to estimate the new controllability and observability. The procedures used for assigning directions to MOS switches are discussed. The algorithms are implemented in LTIME, a CMOS timing analyzer. The techniques are also applied to dynamic power dissipation analysis, of CMOS circuits and are used in predicting chip-level failure rates due to hot-electron effects.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example has been used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST (built-in-self-testing) with different test schedules have been explored. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.<>
{"title":"VLSI design synthesis with testability","authors":"C. Gebotys, M. Elmasry","doi":"10.1109/DAC.1988.14728","DOIUrl":"https://doi.org/10.1109/DAC.1988.14728","url":null,"abstract":"A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom-up and top-down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example has been used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST (built-in-self-testing) with different test schedules have been explored. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131165966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.<>
{"title":"A defect-tolerant and fully testable PLA","authors":"N. Wehn, M. Glesner, K. Caesar, P. Mann, A. Roth","doi":"10.1109/DAC.1988.14729","DOIUrl":"https://doi.org/10.1109/DAC.1988.14729","url":null,"abstract":"The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123040352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An extended true vertical-horizontal-vertical (VHV)-model three-layer channel routing algorithm is described. The algorithm is based on the observation that, after routing a track on either the top or bottom side of the channel, it is possible to define a new channel routing problem and call the router recursively. The routing task then is reduced to making optimal use of a track. Routing of track is done in two steps. For the first step, the authors present a segment selection method, which aims at reducing the channel density. The second step further fills up the track and, at the same time, aims at reducing the heights of the vertical constraint graphs.<>
{"title":"Recursive channel router","authors":"W. Heyns, K. V. Nieuwenhove","doi":"10.1109/DAC.1988.14755","DOIUrl":"https://doi.org/10.1109/DAC.1988.14755","url":null,"abstract":"An extended true vertical-horizontal-vertical (VHV)-model three-layer channel routing algorithm is described. The algorithm is based on the observation that, after routing a track on either the top or bottom side of the channel, it is possible to define a new channel routing problem and call the router recursively. The routing task then is reduced to making optimal use of a track. Routing of track is done in two steps. For the first step, the authors present a segment selection method, which aims at reducing the channel density. The second step further fills up the track and, at the same time, aims at reducing the heights of the vertical constraint graphs.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124752219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present several powerful techniques which allow them to generate efficiently channel routing solutions which are beneficial to further compaction. These techniques can be applied to straight-track compaction as well as to contour-routing compaction and produce very encouraging results. In particular, for D.N. Deutsch's (1985) Difficult Example, they obtained straight-track routing solution with an area 7% less than the best known result after straight-track compaction. The router generated a routing solution using less area than reported results of all well known routers after contour-routing compaction.<>
{"title":"How to obtain more compactable channel routing solutions","authors":"Jingsheng Cong, D. F. Wong","doi":"10.1109/DAC.1988.14838","DOIUrl":"https://doi.org/10.1109/DAC.1988.14838","url":null,"abstract":"The authors present several powerful techniques which allow them to generate efficiently channel routing solutions which are beneficial to further compaction. These techniques can be applied to straight-track compaction as well as to contour-routing compaction and produce very encouraging results. In particular, for D.N. Deutsch's (1985) Difficult Example, they obtained straight-track routing solution with an area 7% less than the best known result after straight-track compaction. The router generated a routing solution using less area than reported results of all well known routers after contour-routing compaction.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches.<>
{"title":"On path selection in combinational logic circuits","authors":"W. Li, S. Reddy, S. Sahni","doi":"10.1109/DAC.1988.14749","DOIUrl":"https://doi.org/10.1109/DAC.1988.14749","url":null,"abstract":"The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A discussion is presented of implementation and extensions of an abstract timing verifier, and in particular, several novel operations and a novel algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to check a design for timing errors when the clock schedule is fixed and known, or to derive spacing constraints between clock edges when only the relative ordering of the clock edges is known. All algorithms are designed to operate on a wide variety of representation of time and delay.<>
{"title":"ATV: an abstract timing verifier","authors":"D. Wallace, C. Séquin","doi":"10.1109/DAC.1988.14751","DOIUrl":"https://doi.org/10.1109/DAC.1988.14751","url":null,"abstract":"A discussion is presented of implementation and extensions of an abstract timing verifier, and in particular, several novel operations and a novel algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to check a design for timing errors when the clock schedule is fixed and known, or to derive spacing constraints between clock edges when only the relative ordering of the clock edges is known. All algorithms are designed to operate on a wide variety of representation of time and delay.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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