Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783067
Markus Ulbricht, Mario Schölzel, T. Koal, H. Vierhaus
This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques, a combination of them in a hierarchical manner is provided. By this, the data path of the VLIW processor can be checked within a very short time and at a fine grained diagnostic level. The results show that the required diagnostic resolution for the used processor model with self-repair capability can be obtained with a relatively small hardware overhead of about 6%.
{"title":"A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors","authors":"Markus Ulbricht, Mario Schölzel, T. Koal, H. Vierhaus","doi":"10.1109/DDECS.2011.5783067","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783067","url":null,"abstract":"This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques, a combination of them in a hierarchical manner is provided. By this, the data path of the VLIW processor can be checked within a very short time and at a fine grained diagnostic level. The results show that the required diagnostic resolution for the used processor model with self-repair capability can be obtained with a relatively small hardware overhead of about 6%.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"56 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120913768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783117
F. Goodarzy, E. Skafidas
Low power consumption and small size transceivers are critical for biomedical instruments and devices specially those that are implanted. In this paper a novel modulation scheme called saturated analog signal (SAS) has been developed that can reduce the power consumption and area of the receiver. The new CMOS receiver is implemented in 65nm technology and operates in the MICS band (402–405 MHz), while consumes 10 µW from a 1 V power supply to deliver 500 Kb/s of data and occupies an area of just 0.6 mm2. This is equivalent to an energy consumption of 20 pJ/b and the design is capable of being fully integrated on single chip solutions for retinal prosthesis and embedded neural applications.
{"title":"A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application","authors":"F. Goodarzy, E. Skafidas","doi":"10.1109/DDECS.2011.5783117","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783117","url":null,"abstract":"Low power consumption and small size transceivers are critical for biomedical instruments and devices specially those that are implanted. In this paper a novel modulation scheme called saturated analog signal (SAS) has been developed that can reduce the power consumption and area of the receiver. The new CMOS receiver is implemented in 65nm technology and operates in the MICS band (402–405 MHz), while consumes 10 µW from a 1 V power supply to deliver 500 Kb/s of data and occupies an area of just 0.6 mm2. This is equivalent to an energy consumption of 20 pJ/b and the design is capable of being fully integrated on single chip solutions for retinal prosthesis and embedded neural applications.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"45 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783075
T. Iwagaki, K. Saluja
Hold-time violations in a scan circuit may occur both in the scan chain and in its combinational logic part. If a hold-time violation occurs on the scan path from one scan cell to another, it is also likely to happen on short functional paths between the two cells, which have clock skew. This paper is intended to indirectly detect hold-time violations on short functional paths using scan shift operations. A greedy approach to scan chain ordering is presented to detect as many hold-time violations as possible using scan shift operations. Extensive experiments are conducted to detect hold-time violations on short functional paths of various lengths by scan shift operations. Experimental results show that many hold-time violations on short functional paths can be detected by choosing an appropriate order of the scan cells in the scan chain.
{"title":"Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations","authors":"T. Iwagaki, K. Saluja","doi":"10.1109/DDECS.2011.5783075","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783075","url":null,"abstract":"Hold-time violations in a scan circuit may occur both in the scan chain and in its combinational logic part. If a hold-time violation occurs on the scan path from one scan cell to another, it is also likely to happen on short functional paths between the two cells, which have clock skew. This paper is intended to indirectly detect hold-time violations on short functional paths using scan shift operations. A greedy approach to scan chain ordering is presented to detect as many hold-time violations as possible using scan shift operations. Extensive experiments are conducted to detect hold-time violations on short functional paths of various lengths by scan shift operations. Experimental results show that many hold-time violations on short functional paths can be detected by choosing an appropriate order of the scan cells in the scan chain.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116737790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783123
L. Nagy, V. Stopjaková
This paper addresses an alternative approach in detecting completion of computation in asynchronous circuits. The proposed method is based on sensing the amount of consumed power supply current. It represents a simple but reliable and effective way of detecting the computation completion in this type of digital systems. The paper presents a novel topology of current sensing circuitry, explanation of the operation as well as simulation results and finally the conclusion.
{"title":"Current sensing methodology for completion detection in self-timed systems","authors":"L. Nagy, V. Stopjaková","doi":"10.1109/DDECS.2011.5783123","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783123","url":null,"abstract":"This paper addresses an alternative approach in detecting completion of computation in asynchronous circuits. The proposed method is based on sensing the amount of consumed power supply current. It represents a simple but reliable and effective way of detecting the computation completion in this type of digital systems. The paper presents a novel topology of current sensing circuitry, explanation of the operation as well as simulation results and finally the conclusion.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783053
S. Kostin, R. Ubar, J. Raik
We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high diagnostic resolution of the proposed approach.
{"title":"Defect-oriented module-level fault diagnosis in digital circuits","authors":"S. Kostin, R. Ubar, J. Raik","doi":"10.1109/DDECS.2011.5783053","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783053","url":null,"abstract":"We propose a hierarchical approach for physical defect diagnosis in combinational or full scan-path digital circuits represented as module networks. As modules we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. Both, cause-effect and effect-cause approaches are exploited intermittently. The higher level fault diagnosis is carried out in two phases. In the first phase, faulty modules are located by cause-effect analysis using high-level faulty module dictionary. The size of the dictionary depends linearly on the number of modules in the circuit. In the second phase, the set of suspected faulty modules is pruned by effect-cause indirect defect reasoning. At the lower level, the physical defects are directly located in suspected faulty modules. The proposed approach to fault diagnosis helps to cope with the growing complexities of digital circuits. The experimental results show high diagnostic resolution of the proposed approach.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114283852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783076
S. Kolodzinski, E. Hrynkiewicz
The paper deals with the problems of decomposition of set of logic functions in Reed-Muller spectral domain. The approach is based on searching of the common sub-functions for as many as possible logic functions. A decomposition is executed in Reed-Muller spectral domain but Reed-Muller spectrum of multi-output logic function does not exist. Therefore the common sub-functions are searched in the form of the same sub-spectrums in Reed-Muller spectrum of each function. For these functions for which a disjoint Ashenhurst or Curtis decomposition does not exist a non-disjoint decomposition is searched. A specification of non specified states is performed to obtain the same sub-spectrum as exists in spectrum of other functions. The examples show that the approach may be profitable.
{"title":"Decomposition of multi-output logic function in Reed-Muller spectral domain","authors":"S. Kolodzinski, E. Hrynkiewicz","doi":"10.1109/DDECS.2011.5783076","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783076","url":null,"abstract":"The paper deals with the problems of decomposition of set of logic functions in Reed-Muller spectral domain. The approach is based on searching of the common sub-functions for as many as possible logic functions. A decomposition is executed in Reed-Muller spectral domain but Reed-Muller spectrum of multi-output logic function does not exist. Therefore the common sub-functions are searched in the form of the same sub-spectrums in Reed-Muller spectrum of each function. For these functions for which a disjoint Ashenhurst or Curtis decomposition does not exist a non-disjoint decomposition is searched. A specification of non specified states is performed to obtain the same sub-spectrum as exists in spectrum of other functions. The examples show that the approach may be profitable.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131175584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783037
D. Ha
Harvesting small scale energy from otherwise wasted ambient energy sources has attracted immense research efforts for battery-powered wireless sensor networks for various applications such as structural health monitoring, industrial condition monitoring and healthcare. The power level which those applications may reach ranges from microwatts to milliwatts. Energy scavenged from ambient sources may be able to recharge or even eliminate the battery to power up those devices perpetually. Sources of energy for harvesting include, but are not limited, to light, thermal gradient, vibration, and radio frequency radiation. The fluctuation and intermittence of these ambient energy sources bring in challenging technical issues to make self-powered systems practical. Energy storage devices like rechargeable batteries or supercapacitors and efficient power management circuitry are indispensable to convert a dynamic environmental energy input into a stable power source. This presentation reviews principles of energy harvesting and practices for small scale energy harvesters and self-powered wireless sensor modules developed recently. Industry trends and possible research issues for further developments are discussed in order to give a technical insight into energy harvesting techniques and their applications.
{"title":"Small scale energy harvesting - principles, practices and future trends","authors":"D. Ha","doi":"10.1109/DDECS.2011.5783037","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783037","url":null,"abstract":"Harvesting small scale energy from otherwise wasted ambient energy sources has attracted immense research efforts for battery-powered wireless sensor networks for various applications such as structural health monitoring, industrial condition monitoring and healthcare. The power level which those applications may reach ranges from microwatts to milliwatts. Energy scavenged from ambient sources may be able to recharge or even eliminate the battery to power up those devices perpetually. Sources of energy for harvesting include, but are not limited, to light, thermal gradient, vibration, and radio frequency radiation. The fluctuation and intermittence of these ambient energy sources bring in challenging technical issues to make self-powered systems practical. Energy storage devices like rechargeable batteries or supercapacitors and efficient power management circuitry are indispensable to convert a dynamic environmental energy input into a stable power source. This presentation reviews principles of energy harvesting and practices for small scale energy harvesters and self-powered wireless sensor modules developed recently. Industry trends and possible research issues for further developments are discussed in order to give a technical insight into energy harvesting techniques and their applications.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131642446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783046
D. Hély, V. Beroulle, Feng Lu, J. R. G. Oya
In this work, we propose to develop and to combine in a same tool functional verification and robustness analysis of IP cores. The overall purpose of this methodology unifying functional verification and robustness analysis is to help designers in getting more quickly “first right time” hardened IP designs. Indeed, re-using the results of the functional verification analysis, i.e. mutation score, will help us to analyze more quickly the IP robustness. In this paper, we discuss about the synthesizable Mutation Function performing the transient fault injection. We focus on its efficiency to model realistic transient faults and to fit with the already existing Aligator platform performing the functional verification analysis of digital IP.
{"title":"Towards an unified IP verification and robustness analysis platform","authors":"D. Hély, V. Beroulle, Feng Lu, J. R. G. Oya","doi":"10.1109/DDECS.2011.5783046","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783046","url":null,"abstract":"In this work, we propose to develop and to combine in a same tool functional verification and robustness analysis of IP cores. The overall purpose of this methodology unifying functional verification and robustness analysis is to help designers in getting more quickly “first right time” hardened IP designs. Indeed, re-using the results of the functional verification analysis, i.e. mutation score, will help us to analyze more quickly the IP robustness. In this paper, we discuss about the synthesizable Mutation Function performing the transient fault injection. We focus on its efficiency to model realistic transient faults and to fit with the already existing Aligator platform performing the functional verification analysis of digital IP.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115163807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783107
M. Taouil, S. Hamdioui
Three-dimensional Stacked IC (3D-SIC) is a promising technology gaining a lot of attention by industry. Such technology promises lower latency, lower power consumption and a smaller footprint as compared to planar ICs. Reducing the overall 3D-SIC manufacturing cost is a major challenge driving the industry. The process of stacking the dies together is an integral part of 3D-SIC manufacturing process; hence, it impacts the overall cost. This paper introduces out-of-order stacking and compares it with the conventional in-order stacking from cost point of view. In-order stacking restricts the stacking of the dies in a bottom-up sequential order, while out-of-order stacking poses no restrictions and the order is free as long as it is realistic. The simulation results show that out-of-order stacking ends up in lower cost than in-order stacking, and that the difference increases for larger stack sizes and lower stacking yield. For example, our case study shows that for a 3D-SIC with a stack size of 6 layers, out-of-order stacking outperforms the in-order one with up to 6% using the optimal test flow.
{"title":"Stacking order impact on overall 3D die-to-wafer Stacked-IC cost","authors":"M. Taouil, S. Hamdioui","doi":"10.1109/DDECS.2011.5783107","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783107","url":null,"abstract":"Three-dimensional Stacked IC (3D-SIC) is a promising technology gaining a lot of attention by industry. Such technology promises lower latency, lower power consumption and a smaller footprint as compared to planar ICs. Reducing the overall 3D-SIC manufacturing cost is a major challenge driving the industry. The process of stacking the dies together is an integral part of 3D-SIC manufacturing process; hence, it impacts the overall cost. This paper introduces out-of-order stacking and compares it with the conventional in-order stacking from cost point of view. In-order stacking restricts the stacking of the dies in a bottom-up sequential order, while out-of-order stacking poses no restrictions and the order is free as long as it is realistic. The simulation results show that out-of-order stacking ends up in lower cost than in-order stacking, and that the difference increases for larger stack sizes and lower stacking yield. For example, our case study shows that for a 3D-SIC with a stack size of 6 layers, out-of-order stacking outperforms the in-order one with up to 6% using the optimal test flow.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132783158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783103
V. Sklyarov, I. Skliarova, D. Mihhailov, A. Sudnitson
The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.
{"title":"High-performance hardware accelerators for sorting and managing priorities","authors":"V. Sklyarov, I. Skliarova, D. Mihhailov, A. Sudnitson","doi":"10.1109/DDECS.2011.5783103","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783103","url":null,"abstract":"The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114224042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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