Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783039
M. Ferringer
Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient conversion and interfacing techniques between these design methodologies arises. In this paper we take a closer look on how such conversion blocks can be built efficiently. We elaborate implementations for signal conversion between three distinct asynchronous design alternatives, discuss their benefits and drawbacks, and provide simulation results. We not only consider cases where both sender and receiver use handshaking protocols for flow control, but also the situation where this kind of lockstep operation is not possible.
{"title":"Conversion and interfacing techniques for asynchronous circuits","authors":"M. Ferringer","doi":"10.1109/DDECS.2011.5783039","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783039","url":null,"abstract":"Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient conversion and interfacing techniques between these design methodologies arises. In this paper we take a closer look on how such conversion blocks can be built efficiently. We elaborate implementations for signal conversion between three distinct asynchronous design alternatives, discuss their benefits and drawbacks, and provide simulation results. We not only consider cases where both sender and receiver use handshaking protocols for flow control, but also the situation where this kind of lockstep operation is not possible.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783078
A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel
As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. In this work, we present a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-up or slow-down. Furthermore, our study shows the degrading influence of supply noise resonance on the path delay. We perform HSPICE simulations for path delay analysis on various technology nodes i.e. 130nm, 90nm, 65nm and 45nm
{"title":"A study of path delay variations in the presence of uncorrelated power and ground supply noise","authors":"A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel","doi":"10.1109/DDECS.2011.5783078","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783078","url":null,"abstract":"As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. In this work, we present a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-up or slow-down. Furthermore, our study shows the degrading influence of supply noise resonance on the path delay. We perform HSPICE simulations for path delay analysis on various technology nodes i.e. 130nm, 90nm, 65nm and 45nm","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114971155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783099
L. Agnola, M. Vladutiu, M. Udrescu, L. Prodan
This paper provides an analysis of the performance and overhead for the Self Adaptive cache Memories mechanism (SAM). SAM is a graceful degradation method applied to set associative cache memories that uses remapping for some memory locations to obtain an increase in performance by means of a switching table. We also discuss how a major increase in performance of over 75% can be achieved, while the overall area also decreases with more than 35%, because of minimizing the entries in the switching table, by adding switching bits.
{"title":"Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm","authors":"L. Agnola, M. Vladutiu, M. Udrescu, L. Prodan","doi":"10.1109/DDECS.2011.5783099","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783099","url":null,"abstract":"This paper provides an analysis of the performance and overhead for the Self Adaptive cache Memories mechanism (SAM). SAM is a graceful degradation method applied to set associative cache memories that uses remapping for some memory locations to obtain an increase in performance by means of a switching table. We also discuss how a major increase in performance of over 75% can be achieved, while the overall area also decreases with more than 35%, because of minimizing the entries in the switching table, by adding switching bits.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117109502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783055
M. Sauer, A. Czutro, Tobias Schubert, Stefan Hillebrecht, I. Polian, B. Becker
Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.
{"title":"SAT-based analysis of sensitisable paths","authors":"M. Sauer, A. Czutro, Tobias Schubert, Stefan Hillebrecht, I. Polian, B. Becker","doi":"10.1109/DDECS.2011.5783055","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783055","url":null,"abstract":"Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122025321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783084
Abdelmajid Bouajila, Johannes Zeppenfeld, W. Stechele, A. Herkersdorf
This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.
{"title":"An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors","authors":"Abdelmajid Bouajila, Johannes Zeppenfeld, W. Stechele, A. Herkersdorf","doi":"10.1109/DDECS.2011.5783084","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783084","url":null,"abstract":"This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125830153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783041
V. Chawla, D. Ha
We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design is presented which detects short duration UWB impulses on its power line. The design has been done in IBM 0.13 um digital CMOS process and has been shown to consume 3.58 mW when operating from 1.2 V supply.
{"title":"Dual use of power lines for data communications in microprocessors","authors":"V. Chawla, D. Ha","doi":"10.1109/DDECS.2011.5783041","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783041","url":null,"abstract":"We proposed power line communication (PLC) through a microprocessor's power distribution network as a novel technique for communicating to any node inside a chip and demonstrated the suitability of Impulse Ultra-Wideband (UWB) communication. Applications of this scheme discussed in this paper exemplify the applicability of this scheme in future microprocessors. Further, data recovery block design is presented which detects short duration UWB impulses on its power line. The design has been done in IBM 0.13 um digital CMOS process and has been shown to consume 3.58 mW when operating from 1.2 V supply.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783081
L. Sterpone, D. Sabena, S. Campagna, M. Reorda
VLIW architectures are widely employed in several embedded signal applications mainly because they offer the opportunity to gain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors became more and more suitable to be employed in various embedded processing systems including safety critical applications such as aerospace, automotive and rail transport. Therefore, techniques to effectively estimate and improve the reliability of VLIW processor are of great interest. Terrestrial safety-critical applications based on newer nano-scale technologies raise increasing concerns about transient errors induced by neutrons. In this paper, we analyze the cross-domain failures affecting redundant mitigation techniques implemented on a statistically scheduled data path VLIW processor and we describe a fault injection analysis of transient faults affecting the r-VEX VLIW processor implemented on an FPGA platform. For a large set of benchmark applications, figures of application performances and errors analysis are provided and commented.
{"title":"Fault injection analysis of transient faults in clustered VLIW processors","authors":"L. Sterpone, D. Sabena, S. Campagna, M. Reorda","doi":"10.1109/DDECS.2011.5783081","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783081","url":null,"abstract":"VLIW architectures are widely employed in several embedded signal applications mainly because they offer the opportunity to gain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors became more and more suitable to be employed in various embedded processing systems including safety critical applications such as aerospace, automotive and rail transport. Therefore, techniques to effectively estimate and improve the reliability of VLIW processor are of great interest. Terrestrial safety-critical applications based on newer nano-scale technologies raise increasing concerns about transient errors induced by neutrons. In this paper, we analyze the cross-domain failures affecting redundant mitigation techniques implemented on a statistically scheduled data path VLIW processor and we describe a fault injection analysis of transient faults affecting the r-VEX VLIW processor implemented on an FPGA platform. For a large set of benchmark applications, figures of application performances and errors analysis are provided and commented.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130956801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783110
L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine
A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.
{"title":"Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling","authors":"L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine","doi":"10.1109/DDECS.2011.5783110","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783110","url":null,"abstract":"A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783119
M. Straka, Jan Kastil, Jaroslav Novotný, Z. Kotásek
In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used. All experiments were done on the Virtex5 and Virtex6 platform.
{"title":"Advanced fault tolerant bus for multicore system implemented in FPGA","authors":"M. Straka, Jan Kastil, Jaroslav Novotný, Z. Kotásek","doi":"10.1109/DDECS.2011.5783119","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783119","url":null,"abstract":"In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used. All experiments were done on the Virtex5 and Virtex6 platform.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126879141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783132
Mohamed Bawadekji, Daniel Große, R. Drechsler
Design and verification of embedded systems at the Electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. They are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.
{"title":"TLM protocol compliance checking at the Electronic System Level","authors":"Mohamed Bawadekji, Daniel Große, R. Drechsler","doi":"10.1109/DDECS.2011.5783132","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783132","url":null,"abstract":"Design and verification of embedded systems at the Electronic System Level (ESL) is common practice. In particular, Transaction Level Modeling (TLM) is the major reason for the success of ESL design. However, when detailed protocols are modeled at lower levels of TLM, the verification of the communication becomes a critical issue. In this paper, we present an approach for protocol compliance checking of new or detailed protocol implementations. They are checked against user-specified protocol sequences. We also analyze the protocol coverage achieved by the testbench and visualize the results on a protocol sequence graph. Experimental results for a SoC model demonstrate the advantages of our method.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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