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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems最新文献

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Dynamic placement applications into Self Adaptive network on FPGA 动态布局在FPGA自适应网络中的应用
P. Honzík, J. Kadlec
The presented work deals with reconfigurable systems with Self Adaptivity based on the FPGA technology. The work is based on partial dynamic reconfiguration of FPGA devices and analyzes Self Adaptive systems, their elements and features. The main part introduces placement algorithms and Step Adaptive algorithm for improving mapping on running network. The tests of algorithm are done on the sets of the test applications.
本文研究了基于FPGA技术的自适应可重构系统。该工作基于FPGA器件的局部动态重构,分析了自适应系统及其组成和特点。主要部分介绍了用于改进运行网络映射的布局算法和步进自适应算法。算法的测试是在测试应用的集合上进行的。
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引用次数: 0
Proof certificates and non-linear arithmetic constraints 证明证书和非线性算术约束
Stefan Kupferschmid, B. Becker, Tino Teige, M. Fränzle
Symbolic methods in computer-aided verification rely heavily on constraint solvers. The correctness and reliability of these solvers are of vital importance in the analysis of safety-critical systems, e.g., in the automotive context. Satisfiability results of a solver can usually be checked by probing the computed solution. This is in general not the case for un-satisfiability results. In this paper, we propose a certification method for unsatisfiability results for mixed Boolean and non-linear arithmetic constraint formulae. Such formulae arise in the analysis of hybrid discrete/continuous systems. Furthermore, we test our approach by enhancing the iSAT constraint solver to generate unsatisfiability proofs, and implemented a tool that can efficiently validate such proofs. Finally, some experimental results showing the effectiveness of our techniques are given.
计算机辅助验证中的符号方法严重依赖约束求解器。这些解算器的正确性和可靠性在安全关键系统的分析中至关重要,例如在汽车环境中。求解器的可满足性结果通常可以通过探测计算解来检验。一般来说,不令人满意的结果并非如此。本文提出了一种布尔和非线性混合算术约束公式不满足结果的证明方法。这样的公式出现在离散/连续混合系统的分析中。此外,我们通过增强iSAT约束求解器来测试我们的方法以生成不满足性证明,并实现了一个可以有效验证这些证明的工具。最后给出了一些实验结果,证明了该方法的有效性。
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引用次数: 8
DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development DODT:使用领域本体增加需求形式化,以改进嵌入式系统开发
S. Farfeleder, T. Moser, A. Krall, T. Stålhane, H. Zojer, C. Panis
In times of ever-growing system complexity and thus increasing possibilities for errors, high-quality requirements are crucial to prevent design errors in later project phases and to facilitate design verification and validation. To ensure and improve the consistency, completeness and correctness of requirements, formal languages have been introduced as an alternative to using natural language (NL) requirement descriptions. However, in many cases existing NL requirements must be taken into account. The formalization of those requirements by now is a primarily manual task, which therefore is both cumbersome and error-prone. We introduce the tool DODT that semi-automatically transforms NL requirements into semi-formal boilerplate requirements. The transformation builds upon a domain ontology (DO) containing knowledge of the problem domain and upon natural language processing techniques. The tool strongly reduced the required manual effort for the transformation. In addition the quality of the requirements was improved.
在系统复杂性不断增长的时代,从而增加了错误的可能性,高质量的需求对于防止后期项目阶段的设计错误以及促进设计验证和确认至关重要。为了确保和改进需求的一致性、完整性和正确性,引入了形式语言作为使用自然语言(NL)需求描述的替代方法。但是,在许多情况下,必须考虑到现有的国家法律规定。到目前为止,这些需求的形式化主要是一项手工任务,因此既麻烦又容易出错。我们引入了工具DODT,它可以半自动地将NL需求转换为半正式的样板需求。转换建立在包含问题领域知识的领域本体(DO)和自然语言处理技术的基础上。该工具大大减少了转换所需的手工工作。此外,需求的质量也得到了提高。
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引用次数: 71
Testing and design-for-testability solutions for 3D integrated circuits 3D集成电路的测试和可测试性设计解决方案
K. Chakrabarty
Three-dimensional integrated circuits (3D ICs) promise to overcome barriers in interconnect scaling, thereby offering an opportunity to get higher performance using CMOS technology. Despite these benefits, testing remains a major obstacle that hinders the adoption of 3D integration. Test techniques and design-for-testability (DfT) solutions for 3D ICs have remained largely unexplored in the research community, even though experts in industry have identified a number of test challenges related to the lack of probe access for wafers, test access to modules in stacked wafers/dies, thermal concerns, test economics, and new defects arising from unique processing steps such as wafer thinning, alignment, and bonding. In this embedded tutorial, the speaker will present an overview of 3D integration, its unique processing and assembly steps, testing and DfT challenges, and some of the solutions being advocated for these challenges. The speaker will focus on proposals for pre-bond testing of dies and TSVs, DfT innovations related to the optimization of die wrappers, test scheduling solutions, and access to dies and inter-die interconnects during stack testing. Time permitting, the speaker will also highlight recent work on comprehensive cost modeling for 3D ICs, which includes the cost of design, manufacture, testing, and test flows.
三维集成电路(3D ic)有望克服互连扩展的障碍,从而提供了使用CMOS技术获得更高性能的机会。尽管有这些好处,测试仍然是阻碍采用3D集成的主要障碍。3D集成电路的测试技术和可测试性设计(DfT)解决方案在研究界仍未得到很大的探索,尽管行业专家已经确定了许多测试挑战,这些挑战涉及晶圆缺乏探针访问、堆叠晶圆/模具中模块的测试访问、热问题、测试经济性以及晶圆变薄、对准和粘合等独特加工步骤产生的新缺陷。在这个嵌入式教程中,演讲者将介绍3D集成的概述,其独特的加工和组装步骤,测试和DfT挑战,以及一些正在倡导这些挑战的解决方案。演讲者将重点介绍模具和tsv的粘合前测试,与模具包装优化相关的DfT创新,测试调度解决方案,以及在堆栈测试期间访问模具和模具间互连的建议。在时间允许的情况下,演讲者还将重点介绍最近在3D集成电路综合成本建模方面的工作,包括设计、制造、测试和测试流程的成本。
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引用次数: 0
Characterization of digital cells for statistical test 用于统计试验的数字细胞的特性
Fabian Hopsch, M. Lindig, B. Straube, W. Vermeiren
Integrated circuits necessitate high quality and high yield. Defects and parameter variations are a main issue affecting both aspects. In this paper a method for characterization for statistical test is presented. The characterization is carried out for a set of digital cells using Monte Carlo fault simulation at electrical level. The results show that only a small amount of faults are being manifested as stuck-at faults. Many faults lead to a mix of different behaviours for various test sequences and parameter configurations. For a digital cell, the necessary test sequences for detecting all detectable faults are derived from the simulation results. Since the effort for the characterization is high, first investigations to reduce this effort are presented.
集成电路要求高质量和高成品率。缺陷和参数变化是影响这两个方面的主要问题。本文提出了一种统计检验的表征方法。利用蒙特卡罗故障模拟在电水平上对一组数字单元进行了表征。结果表明,只有少数断层表现为卡滞断层。许多故障导致各种测试序列和参数配置的不同行为的混合。对于数字单元,从仿真结果中导出了检测所有可检测故障所需的测试序列。由于表征的工作量很大,因此提出了减少这种工作量的初步研究。
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引用次数: 2
Low-complexity integrated circuit aging monitor 低复杂度集成电路老化监视器
A. Simevski, R. Kraemer, M. Krstic
Integrated circuit aging effects are more and more pronounced with the continuous technological downscaling. These effects degrade circuit operation which is mainly observed as increased input-to-output delay of circuit components. Eventually, the circuit falls out of its specifications. Countermeasures are needed to prevent or reduce such degradation. Aging monitoring can be very beneficial since it can predict circuit failure and/or activate mechanisms to avoid failure. Most of the present aging monitors are based on reporting abnormal input-to-output signal delays on the critical path of the circuit. However, present approaches introduce additional circuit complexity, use complicated analog design, use non-standard cells etc. We propose a low-complexity aging monitor based on standard library cells, offering simplicity and flexibility of its design, integration and use. The designer could instantiate many monitors throughout the integrated circuit. The user can simply read the “aging code” placed in a register in each monitor and determine the “age” of the circuit, predict a circuit failure and/or take an appropriate action. This is especially useful in microprocessors which are designed with dependability in mind.
随着集成电路技术规模的不断缩小,集成电路的老化效应越来越明显。这些影响降低了电路的运行,主要表现为电路元件的输入输出延迟增加。最终,电路超出了它的规格。需要采取对策来防止或减少这种退化。老化监测是非常有益的,因为它可以预测电路故障和/或激活机制以避免故障。目前大多数老化监测都是基于报告电路关键路径上的异常输入输出信号延迟。然而,目前的方法引入了额外的电路复杂性,使用复杂的模拟设计,使用非标准单元等。我们提出了一种基于标准库单元的低复杂度老化监测仪,其设计、集成和使用简单灵活。设计者可以在整个集成电路中实例化许多监视器。用户可以简单地读取放置在每个监视器的寄存器中的“老化代码”,并确定电路的“年龄”,预测电路故障和/或采取适当的行动。这对于在设计时考虑到可靠性的微处理器尤其有用。
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引用次数: 13
Test vector overlapping based compression tool for narrow test access mechanism 基于测试向量重叠的窄测试访问机制压缩工具
Jiri Jenícek, M. Rozkovec, O. Novák
This paper describes an algorithm, which utilizes a test data compression method based on test vector overlapping to compact and compress test patterns. The algorithm takes deterministic test vectors previously generated in an ATPG and compresses them by reordering and overlapping them. It is able to speed up the test generation process by using distributed ATPG processing and compress test data for various fault models. Independency of the algorithm on used ATPG is discussed and verified, the compressor is able to cooperate with industry workflow tools using Verilog and STIL formats. The compressor preprocesses the input data to determine the degree of random test resistance for each fault. This optional step allows to rearrange the test vectors more efficiently and results to 10% compression ratio improvement in average.
本文介绍了一种利用基于测试向量重叠的测试数据压缩方法对测试模式进行压缩的算法。该算法采用先前在ATPG中生成的确定性测试向量,并通过重新排序和重叠对其进行压缩。采用分布式ATPG处理,可以加快测试生成过程,并对各种故障模型的测试数据进行压缩。讨论并验证了该算法在ATPG上的独立性,压缩机能够与使用Verilog和STIL格式的行业工作流工具协同工作。压缩机对输入数据进行预处理,以确定每个故障的随机测试电阻的程度。这个可选步骤允许更有效地重新排列测试向量,结果平均压缩比提高10%。
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引用次数: 6
Advanced rectifier and driver for analog VU meter 先进的整流器和驱动模拟VU仪表
M. Pospisilik, M. Adamek
This paper deals with a construction and practical testing of a VU meter driver that includes an accurate rectifier and logarithmic driver of a pointer-type gauge. The logarithm is taken from the rectified signal by employing a capacitor discharge voltage curve. The appropriate circuit was built and tested and the results are also discussed in this article.
本文介绍了一种包括精确整流器和指针式量规的对数驱动器的VU仪表驱动器的构造和实际测试。利用电容放电电压曲线从整流信号中取对数。本文搭建了相应的电路并进行了测试,并对测试结果进行了讨论。
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引用次数: 0
SiGe BiCMOS platform - baseline technology for More Than Moore process module integration SiGe BiCMOS平台-超过摩尔过程模块集成的基线技术
B. Tillack
Future silicon based integrated circuits technology is targeting on reduced transistor dimensions, increased transistor counts and increased operating frequencies. By reaching the nanometer scale region lateral and vertical structures have to be processed which are close to atomic dimensions (ITRS “More Moore” approach). Moreover, emerging research devices and technologies are under investigation to extend the CMOS technology further on or to evaluate solutions for beyond Si CMOS technologies like introducing Ge or III–V material channel replacement. According to the ITRS the alternative “More Than Moore” approach is targeting on diversification by combining different technologies based on a reasonable scaling level. The paper gives an overview of the “More than Moore” strategy based on examples of IHP's SiGe BiCMOS technology. SiGe BiCMOS technologies combine high speed SiGe HBTs, computing power of CMOS, and high-quality passives on a single chip. RF performance of HBTs has been improved a lot over the years enabling mm-wave applications like automotive radar (77 GHz), high data rate fiber links (>100 Gb/s), and Gb/s wireless links (60 GHz, 122 GHz,). Research activities are targeting HBTs allowing THz frequencies (EU FP 7 project DOTFIVE). In a “More than Moore” approach the functionality of the BiCMOS technology is extended by integrating optical components (Si Photonics) and MEMS structures. Moreover, the monolithic or hybrid hetero-integration of Si and III/V compound semiconductor technologies are under investigation enabling new System-on-Chip-solutions.
未来基于硅的集成电路技术的目标是缩小晶体管尺寸,增加晶体管数量和提高工作频率。为了达到纳米尺度,必须处理接近原子尺寸的横向和纵向结构(ITRS“More Moore”方法)。此外,新兴的研究设备和技术正在研究中,以进一步扩展CMOS技术或评估超越Si CMOS技术的解决方案,如引入Ge或III-V材料通道替代。根据ITRS的说法,另一种“超越摩尔”的方法是在合理的规模水平上通过结合不同的技术来实现多样化。本文以IHP的SiGe BiCMOS技术为例,概述了“超越摩尔”战略。SiGe BiCMOS技术将高速SiGe hbt、CMOS的计算能力和高质量无源结合在单个芯片上。多年来,hbt的射频性能得到了很大改善,可以实现毫米波应用,如汽车雷达(77 GHz),高数据速率光纤链路(>100 Gb/s)和Gb/s无线链路(60 GHz, 122 GHz,)。研究活动的目标是允许太赫兹频率的hbt(欧盟fp7项目DOTFIVE)。在“超越摩尔”的方法中,BiCMOS技术的功能通过集成光学元件(Si Photonics)和MEMS结构得到扩展。此外,硅和III/V化合物半导体技术的单片或混合异质集成正在研究中,从而实现新的片上系统解决方案。
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引用次数: 2
Power consumption traces realignment to improve differential power analysis 功耗跟踪调整,以改进差分功率分析
G. D. Natale, M. Flottes, B. Rouzeyre, M. Valka, Denis Réal
Cryptographic devices can be subject to side-channel attacks. Among those attacks, Differential Power Analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature. However, the effectiveness of these counter measures is still evaluated by resort-ing to intensive DPA simulations and constitutes a very time-consuming design task. In this paper we show that the knowledge of the structure of the circuit can be exploited to improve performances of the DPA. We propose to realign power consumption traces according timing information (i.e., path delays). We show the usefulness of the proposed method by comparing the efficiency of classic DPA w.r.t. timing aware DPA.
加密设备可能会受到侧信道攻击。在这些攻击中,差分功率分析(DPA)已被证明是非常有效且易于执行的。文献中提出了几种对策。然而,这些对抗措施的有效性仍然是通过密集的DPA模拟来评估的,并且构成了一个非常耗时的设计任务。在本文中,我们证明了可以利用电路结构的知识来提高DPA的性能。我们建议根据时序信息(即路径延迟)重新调整功耗轨迹。通过比较经典的时间感知DPA的效率,证明了该方法的有效性。
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引用次数: 3
期刊
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
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