Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783063
Jakub Kopanski, W. Pleskacz, D. Pienkowski
In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.
{"title":"A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology","authors":"Jakub Kopanski, W. Pleskacz, D. Pienkowski","doi":"10.1109/DDECS.2011.5783063","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783063","url":null,"abstract":"In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"983 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123087171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783130
Anton Karputkin, R. Ubar, M. Tombak, J. Raik
The paper proposes a novel method for probabilistic equivalence checking of digital systems. The method is based on representing the high-level decision diagrams as the model of digital systems by the sets of characteristic polynomials. It is shown that this representation is canonical, i.e. the sets of polynomials for equivalent diagrams are the same up to the names of the variables. However, computing the full set of polynomials is unfeasible for large diagrams as it demands checking all assignments to the control variables. In order to cope with this problem we have developed a polynomial algorithm for probabilistic equivalence checking.
{"title":"Probabilistic equivalence checking based on high-level decision diagrams","authors":"Anton Karputkin, R. Ubar, M. Tombak, J. Raik","doi":"10.1109/DDECS.2011.5783130","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783130","url":null,"abstract":"The paper proposes a novel method for probabilistic equivalence checking of digital systems. The method is based on representing the high-level decision diagrams as the model of digital systems by the sets of characteristic polynomials. It is shown that this representation is canonical, i.e. the sets of polynomials for equivalent diagrams are the same up to the names of the variables. However, computing the full set of polynomials is unfeasible for large diagrams as it demands checking all assignments to the control variables. In order to cope with this problem we have developed a polynomial algorithm for probabilistic equivalence checking.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123160477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783097
D. Modrzyk, M. Staworko
Article presents a methodology of JPEG2000 compression system verification based on a rate and distortion curve analysis. In the paper issues of subjective and objective image quality metrics are discussed, with special focus on “full-reference” methods. Authors propose division of the test images, into several groups, of similar spatial frequency content and the same resolution. Performed experiments revealed normal distribution of PSNR and deltaPSNR random variables, defined for reconstructed images. The elaborated methodology takes advantage of the normal distribution's three-sigma rule to smart classification of failed tests.
{"title":"Verification of JPEG2000 encoder based on rate and distortion curve analysis","authors":"D. Modrzyk, M. Staworko","doi":"10.1109/DDECS.2011.5783097","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783097","url":null,"abstract":"Article presents a methodology of JPEG2000 compression system verification based on a rate and distortion curve analysis. In the paper issues of subjective and objective image quality metrics are discussed, with special focus on “full-reference” methods. Authors propose division of the test images, into several groups, of similar spatial frequency content and the same resolution. Performed experiments revealed normal distribution of PSNR and deltaPSNR random variables, defined for reconstructed images. The elaborated methodology takes advantage of the normal distribution's three-sigma rule to smart classification of failed tests.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124100532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783122
Jeong-Ki Kim, Jihoon Jeong, D. Ha, Hyung-Soo Lee
This paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. The first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. The circuit dissipates only 230 µW and achieves low phase noise of −127 dBc/Hz@1MHz. The second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). The circuit exhibits a moderate power consumption of 960 µW and achieves very low phase noise of −138 dBc/Hz@1MHz.
{"title":"Low-power quadrature VCO design for medical implant communication service","authors":"Jeong-Ki Kim, Jihoon Jeong, D. Ha, Hyung-Soo Lee","doi":"10.1109/DDECS.2011.5783122","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783122","url":null,"abstract":"This paper presents two different implementations of a low-power quadrature frequency source generator for medical implant communication service (MICS) applications. The first circuit uses a current-reuse VCO running at double the target frequency followed by a divide-by-two frequency divider. The circuit dissipates only 230 µW and achieves low phase noise of −127 dBc/Hz@1MHz. The second one adopts a parallel-coupling scheme to combine two current-reuse VCOs (P-QVCO). The circuit exhibits a moderate power consumption of 960 µW and achieves very low phase noise of −138 dBc/Hz@1MHz.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783105
Jiri Tobola, J. Korenek
With the growing speed of computer networks, the core routers have to increase performance of longest prefix match (LPM) operation on IP address. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. In this paper we propose a new Hast-Tree Bitmap algorithm for fast longest prefix match for both IPv4 and IPv6 networks. The algorithm is able to achieve high throughput for a long IPv6 addresses by fast hash function which is used to jump over the sparse part of the IP prefix tree. The proposed algorithm was mapped to the highly pipelined hardware architecture, which offers well balanced resource requirements for IPv6 look-up and is able to achieve a wire-speed throughput for 100 Gbps networks.
{"title":"Effective hash-based IPv6 longest prefix match","authors":"Jiri Tobola, J. Korenek","doi":"10.1109/DDECS.2011.5783105","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783105","url":null,"abstract":"With the growing speed of computer networks, the core routers have to increase performance of longest prefix match (LPM) operation on IP address. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. In this paper we propose a new Hast-Tree Bitmap algorithm for fast longest prefix match for both IPv4 and IPv6 networks. The algorithm is able to achieve high throughput for a long IPv6 addresses by fast hash function which is used to jump over the sparse part of the IP prefix tree. The proposed algorithm was mapped to the highly pipelined hardware architecture, which offers well balanced resource requirements for IPv6 look-up and is able to achieve a wire-speed throughput for 100 Gbps networks.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122495453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783090
M. Wirnshofer, L. Heiß, G. Georgakos, D. Schmitt-Landsiedel
In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. The AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this task, we propose a Pre-Error flip-flop, that is capable of detecting late data transitions - so-called pre-errors. We provide an in-depth analysis, that is based on a Markov model, to describe the closed loop voltage regulation. We simulated the power saving potential compared to the worst-case design and obtained a reduction of 13.5% in active energy for a negligible error rate of 1E-15. Moreover, we illustrate the opportunity to further reduce the power consumption when tolerating higher error rates. This way, our approach can gain the optimal power saving for a given allowed failure probability.
{"title":"A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring","authors":"M. Wirnshofer, L. Heiß, G. Georgakos, D. Schmitt-Landsiedel","doi":"10.1109/DDECS.2011.5783090","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783090","url":null,"abstract":"In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. The AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this task, we propose a Pre-Error flip-flop, that is capable of detecting late data transitions - so-called pre-errors. We provide an in-depth analysis, that is based on a Markov model, to describe the closed loop voltage regulation. We simulated the power saving potential compared to the worst-case design and obtained a reduction of 13.5% in active energy for a negligible error rate of 1E-15. Moreover, we illustrate the opportunity to further reduce the power consumption when tolerating higher error rates. This way, our approach can gain the optimal power saving for a given allowed failure probability.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783094
Zdenek Prikryl, J. Kroustek, Tomás Hruska, D. Kolář
The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.
{"title":"Fast just-in-time translated simulator for ASIP design","authors":"Zdenek Prikryl, J. Kroustek, Tomás Hruska, D. Kolář","doi":"10.1109/DDECS.2011.5783094","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783094","url":null,"abstract":"The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130957650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783091
A. Marchlewski, H. Zimmermann, I. Jonak-Auer, E. Wachmann
In this work we present the usability of the translinear loop topology as frontend sensing circuit for broadband OEIC chip design in a 0.35µm SiGe BiCMOS technology. The result is a fully monolithically integrated 1-Gbps optical receiver with a sensitivity of −20dBm at 675nm in a mature silicon-based technology, which is appropriate e. g. as a plastic optical fiber (POF) receiver or generally as receiver in short-range optical interconnects.
在这项工作中，我们提出了在0.35 μ m SiGe BiCMOS技术中，作为宽带OEIC芯片设计前端传感电路的非线性环路拓扑的可用性。结果是一个完全单片集成的1 gbps光接收器，在675nm处具有- 20dBm的灵敏度，采用成熟的硅基技术，适合作为塑料光纤(POF)接收器或通常作为短距离光互连的接收器。
{"title":"Receiver OEIC using a bipolar translinear loop","authors":"A. Marchlewski, H. Zimmermann, I. Jonak-Auer, E. Wachmann","doi":"10.1109/DDECS.2011.5783091","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783091","url":null,"abstract":"In this work we present the usability of the translinear loop topology as frontend sensing circuit for broadband OEIC chip design in a 0.35µm SiGe BiCMOS technology. The result is a fully monolithically integrated 1-Gbps optical receiver with a sensitivity of −20dBm at 675nm in a mature silicon-based technology, which is appropriate e. g. as a plastic optical fiber (POF) receiver or generally as receiver in short-range optical interconnects.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123910016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783059
T. Iizuka, K. Asada
This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and a oscillation frequency during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.
{"title":"An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator","authors":"T. Iizuka, K. Asada","doi":"10.1109/DDECS.2011.5783059","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783059","url":null,"abstract":"This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and a oscillation frequency during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121397881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783121
V. Kosar, J. Korenek
Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.
{"title":"Reduction of FPGA resources for regular expression matching by relation similarity","authors":"V. Kosar, J. Korenek","doi":"10.1109/DDECS.2011.5783121","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783121","url":null,"abstract":"Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116558504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：