Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783069
P. Dabal, R. Pelka
This paper presents results of studies on the implementation of pseudo-random bit generators based on a nonlinear dynamic chaotic system. Several solutions have been investigated, using different computing precision and various implementation of arithmetic operations. The results of the second level NIST tests for randomness of the proposed pseudo-random bit generators (PRBGs) are presented, that proved good cryptographic properties of the presented PRBGs. The generators described in this paper can be used for key generation in stream ciphers in secure, real-time transmission of digital signals, including audio-video applications.
{"title":"A chaos-based pseudo-random bit generator implemented in FPGA device","authors":"P. Dabal, R. Pelka","doi":"10.1109/DDECS.2011.5783069","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783069","url":null,"abstract":"This paper presents results of studies on the implementation of pseudo-random bit generators based on a nonlinear dynamic chaotic system. Several solutions have been investigated, using different computing precision and various implementation of arithmetic operations. The results of the second level NIST tests for randomness of the proposed pseudo-random bit generators (PRBGs) are presented, that proved good cryptographic properties of the presented PRBGs. The generators described in this paper can be used for key generation in stream ciphers in secure, real-time transmission of digital signals, including audio-video applications.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115764081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783102
V. Gautam, K. C. Ray, P. Haddow
Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2n (n=6, 7…13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.
{"title":"Hardware efficient design of Variable Length FFT Processor","authors":"V. Gautam, K. C. Ray, P. Haddow","doi":"10.1109/DDECS.2011.5783102","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783102","url":null,"abstract":"Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2n (n=6, 7…13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115430980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783108
Yiorgos I. Bontzios, M. Dimopoulos, A. Hatzopoulos
A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.
{"title":"A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits","authors":"Yiorgos I. Bontzios, M. Dimopoulos, A. Hatzopoulos","doi":"10.1109/DDECS.2011.5783108","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783108","url":null,"abstract":"A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130953819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783093
Yaseen Zaidi, Sumit Adhikari, C. Grimm
SystemC AMS offers high abstraction and simulation speed through models of computation and language features such as static scheduling, constant time stepping, linear solver and dataflow paradigm. We demonstrate that such rich expressiveness can render non-ideal behavior in system level description. Design exploration and refinement from system level down to cycle accurate or circuit level is also demonstrated. The main contribution is that the fine grain characterization can start at system level design.
{"title":"Abstract modeling and simulation based selective estimation","authors":"Yaseen Zaidi, Sumit Adhikari, C. Grimm","doi":"10.1109/DDECS.2011.5783093","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783093","url":null,"abstract":"SystemC AMS offers high abstraction and simulation speed through models of computation and language features such as static scheduling, constant time stepping, linear solver and dataflow paradigm. We demonstrate that such rich expressiveness can render non-ideal behavior in system level description. Design exploration and refinement from system level down to cycle accurate or circuit level is also demonstrated. The main contribution is that the fine grain characterization can start at system level design.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122435524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783087
Ke Jiang, P. Eles, Zebo Peng
In this paper we consider distributed embedded systems in which privacy or confidentiality of the internal communication is critical, and present an approach to optimizing cryptographic algorithms under strict timing constraints. We have developed a technique to search for the best system-affordable cryptographic protection for the messages transmitted over the internal communication bus. Towards this, we formulate the optimization technique in Constraint Logic Programming (CLP), which returns optimal results. However, CLP executions are computationally expensive and hence, we propose an efficient heuristic as an alternative. Extensive experiments demonstrate the efficiency of the proposed heuristic approach.
{"title":"Optimization of message encryption for distributed embedded systems with real-time constraints","authors":"Ke Jiang, P. Eles, Zebo Peng","doi":"10.1109/DDECS.2011.5783087","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783087","url":null,"abstract":"In this paper we consider distributed embedded systems in which privacy or confidentiality of the internal communication is critical, and present an approach to optimizing cryptographic algorithms under strict timing constraints. We have developed a technique to search for the best system-affordable cryptographic protection for the messages transmitted over the internal communication bus. Towards this, we formulate the optimization technique in Constraint Logic Programming (CLP), which returns optimal results. However, CLP executions are computationally expensive and hence, we propose an efficient heuristic as an alternative. Extensive experiments demonstrate the efficiency of the proposed heuristic approach.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121128291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783129
Mathias Soeken, U. Kühne, Martin Freibothe, G. Fey, R. Drechsler
The automatic verification of designs is a challenging task and of high interest due to increasing time-to-market constraints. In this paper, we focus on the verification of bus bridges which are used in many hardware systems to connect two buses running different protocols. We developed an approach to assist the automatic generation of properties from the protocol specification for the formal verification of bus bridges. The technical contribution is that the final set of the verification suite is functionally complete in respect to the underlying verification tool which shows the absence of any verification holes. The approach uses an abstract model of bus bridges in terms of state machines which enables a generic work flow. In experimental evaluations we applied the approach to bus bridges based on the OCP/IP protocol family.
{"title":"Automatic property generation for the formal verification of bus bridges","authors":"Mathias Soeken, U. Kühne, Martin Freibothe, G. Fey, R. Drechsler","doi":"10.1109/DDECS.2011.5783129","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783129","url":null,"abstract":"The automatic verification of designs is a challenging task and of high interest due to increasing time-to-market constraints. In this paper, we focus on the verification of bus bridges which are used in many hardware systems to connect two buses running different protocols. We developed an approach to assist the automatic generation of properties from the protocol specification for the formal verification of bus bridges. The technical contribution is that the final set of the verification suite is functionally complete in respect to the underlying verification tool which shows the absence of any verification holes. The approach uses an abstract model of bus bridges in terms of state machines which enables a generic work flow. In experimental evaluations we applied the approach to bus bridges based on the OCP/IP protocol family.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783050
D. Arbet, J. Brenkus, G. Gyepes, V. Stopjaková
A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.
{"title":"Increasing the efficiency of analog OBIST using on-chip compensation of technology variations","authors":"D. Arbet, J. Brenkus, G. Gyepes, V. Stopjaková","doi":"10.1109/DDECS.2011.5783050","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783050","url":null,"abstract":"A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"34 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124145331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783134
R. Ruzicka, Václav Simek, L. Sekanina
The paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. These experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (Vdd). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by Vdd, but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.
{"title":"Behavior of CMOS polymorphic circuits in high temperature environment","authors":"R. Ruzicka, Václav Simek, L. Sekanina","doi":"10.1109/DDECS.2011.5783134","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783134","url":null,"abstract":"The paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. These experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (Vdd). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by Vdd, but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127845251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783115
Urban Ingelsson, Shih-Yen Chang, E. Larsson
In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wear-out monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.
{"title":"Measurement point selection for in-operation wear-out monitoring","authors":"Urban Ingelsson, Shih-Yen Chang, E. Larsson","doi":"10.1109/DDECS.2011.5783115","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783115","url":null,"abstract":"In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wear-out monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783082
Michael Augustin, M. Gössel, R. Kraemer
Circuits implementing the concept of Selective Fault Tolerance according to [1] are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.
{"title":"Implementation of Selective Fault Tolerance with conventional synthesis tools","authors":"Michael Augustin, M. Gössel, R. Kraemer","doi":"10.1109/DDECS.2011.5783082","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783082","url":null,"abstract":"Circuits implementing the concept of Selective Fault Tolerance according to [1] are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128468342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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