Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783044
Sumit Adhikari, Muhammad Farooq, Jan Haase, C. Grimm
Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, kBT/CS noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.
{"title":"High performance adaptive sensor interface design through model based estimation of analog non-idealities","authors":"Sumit Adhikari, Muhammad Farooq, Jan Haase, C. Grimm","doi":"10.1109/DDECS.2011.5783044","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783044","url":null,"abstract":"Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, kBT/CS noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128661501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783111
Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez
The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.
{"title":"On using a SPICE-like TSTAC™ eFlash model for design and test","authors":"Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez","doi":"10.1109/DDECS.2011.5783111","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783111","url":null,"abstract":"The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123760649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783109
M. D. Carvalho, P. Bernardi, M. Reorda, Nicola Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, Marco Terzi
This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.
{"title":"Optimized embedded memory diagnosis","authors":"M. D. Carvalho, P. Bernardi, M. Reorda, Nicola Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, Marco Terzi","doi":"10.1109/DDECS.2011.5783109","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783109","url":null,"abstract":"This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133633025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783077
Hagen Sämrow, C. Cornelius, Philipp Gorski, J. Salzmann, Andreas Tockhorn, D. Timmermann
Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.
{"title":"Functional enhancements of TMR for power efficient and error resilient ASIC designs","authors":"Hagen Sämrow, C. Cornelius, Philipp Gorski, J. Salzmann, Andreas Tockhorn, D. Timmermann","doi":"10.1109/DDECS.2011.5783077","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783077","url":null,"abstract":"Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783083
T. Koal, H. Vierhaus
Reliability and the mean lifetime are major aspects in today's semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Built-in self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.
{"title":"Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair","authors":"T. Koal, H. Vierhaus","doi":"10.1109/DDECS.2011.5783083","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783083","url":null,"abstract":"Reliability and the mean lifetime are major aspects in today's semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Built-in self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127624867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783118
G. Gyepes, J. Brenkus, D. Arbet, V. Stopjaková
The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.
{"title":"Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies","authors":"G. Gyepes, J. Brenkus, D. Arbet, V. Stopjaková","doi":"10.1109/DDECS.2011.5783118","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783118","url":null,"abstract":"The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783058
Jinmyoung Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada
This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
{"title":"Decoupling capacitance boosting for on-chip resonant supply noise reduction","authors":"Jinmyoung Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada","doi":"10.1109/DDECS.2011.5783058","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783058","url":null,"abstract":"This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783098
C. Bernardeschi, Luca Cassano, A. Domenici
We describe a simulation-based fault injection technique for calculating the probability of failures caused by SEUs in the configuration memory of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the Stochastic Activity Networks (SAN) formalism. We validate our method by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed technique by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.
{"title":"Failure probability of SRAM-FPGA systems with Stochastic Activity Networks","authors":"C. Bernardeschi, Luca Cassano, A. Domenici","doi":"10.1109/DDECS.2011.5783098","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783098","url":null,"abstract":"We describe a simulation-based fault injection technique for calculating the probability of failures caused by SEUs in the configuration memory of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the Stochastic Activity Networks (SAN) formalism. We validate our method by reproducing the results presented in other studies for some representative combinatorial circuits, and we explore the applicability of the proposed technique by analysing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121914217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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