Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783085
V. Pus, Michal Kajan, J. Korenek
Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of network security attacks.
{"title":"Hardware architecture for packet classification with prefix coloring","authors":"V. Pus, Michal Kajan, J. Korenek","doi":"10.1109/DDECS.2011.5783085","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783085","url":null,"abstract":"Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of network security attacks.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783073
Oliver Stecklina, F. Vater, T. Basmer, Erik Bergmann, Hannes Menzel
Modern, energy-efficient sensor nodes cover a wide variety of application scenarios. For a fast adapting of these devices to new requirements a concurrent development process of software and hardware extensions must be feasible. Here we present a Hybrid Simulation Environment (HSE) that combines a cycle accurate simulator for MSP microcontrollers written in Java and SystemC, which allows description of hardware at reasonable abstraction level. The HSE significantly speeds up the simulation of new components compared to conventional simulation engines.
{"title":"Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC","authors":"Oliver Stecklina, F. Vater, T. Basmer, Erik Bergmann, Hannes Menzel","doi":"10.1109/DDECS.2011.5783073","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783073","url":null,"abstract":"Modern, energy-efficient sensor nodes cover a wide variety of application scenarios. For a fast adapting of these devices to new requirements a concurrent development process of software and hardware extensions must be feasible. Here we present a Hybrid Simulation Environment (HSE) that combines a cycle accurate simulator for MSP microcontrollers written in Java and SystemC, which allows description of hardware at reasonable abstraction level. The HSE significantly speeds up the simulation of new components compared to conventional simulation engines.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127860302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783100
Thilo Ohlemueller, Markus Petri
In this paper we investigate the problem of multiple multiplexing DA and AD converters in respect to the sample synchronicity. Different proposals for solution are presented. We show a method to synchronize multiple multiplexed high speed DA and AD converters in FPGAs. The method determines the phase difference between the data clocks of two DA/AD converters, but avoids shifting the input/output data and dealing with multiple clock domains. Specific hardware setup and FPGA implementation details are analyzed and taken into account as well.
{"title":"Sample synchronization of multiple multiplexed DA and AD converters in FPGAs","authors":"Thilo Ohlemueller, Markus Petri","doi":"10.1109/DDECS.2011.5783100","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783100","url":null,"abstract":"In this paper we investigate the problem of multiple multiplexing DA and AD converters in respect to the sample synchronicity. Different proposals for solution are presented. We show a method to synchronize multiple multiplexed high speed DA and AD converters in FPGAs. The method determines the phase difference between the data clocks of two DA/AD converters, but avoids shifting the input/output data and dealing with multiple clock domains. Specific hardware setup and FPGA implementation details are analyzed and taken into account as well.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129193723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783095
Krzysztof Siwiec, T. Borejko, W. Pleskacz
In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. Thanks to these features the created tool is a valuable aid for PLL designer on all design steps.
{"title":"CAD tool for PLL Design","authors":"Krzysztof Siwiec, T. Borejko, W. Pleskacz","doi":"10.1109/DDECS.2011.5783095","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783095","url":null,"abstract":"In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. Thanks to these features the created tool is a valuable aid for PLL designer on all design steps.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114148455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783136
André Seffrin, S. Huss
Dynamic partial reconfiguration enables the reconfiguration of hardware devices at run-time, which saves resources, but introduces additional design complexity. Various methods exist for the specification of reconfiguration schedules, which are either too simple for the description of complex processes, or are inherently difficult to verify. We employ a variant of the π-calculus for modelling dynamic partial reconfiguration. The π-calculus is a process algebra originally constructed for modelling communicating systems, but can be repurposed as a scheduling method for dynamic partial reconfiguration on FPGA devices. In order to apply this type of scheduling for the design of hardware systems, it has to be determined how to allocate the scheduled tasks on the device. By use of a verification tool for the π-calculus, constraints can be extracted from a given system specification. These constraints form the basis to derive the placement of the reconfigurable areas in an automatic fashion.
{"title":"Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms","authors":"André Seffrin, S. Huss","doi":"10.1109/DDECS.2011.5783136","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783136","url":null,"abstract":"Dynamic partial reconfiguration enables the reconfiguration of hardware devices at run-time, which saves resources, but introduces additional design complexity. Various methods exist for the specification of reconfiguration schedules, which are either too simple for the description of complex processes, or are inherently difficult to verify. We employ a variant of the π-calculus for modelling dynamic partial reconfiguration. The π-calculus is a process algebra originally constructed for modelling communicating systems, but can be repurposed as a scheduling method for dynamic partial reconfiguration on FPGA devices. In order to apply this type of scheduling for the design of hardware systems, it has to be determined how to allocate the scheduled tasks on the device. By use of a verification tool for the π-calculus, constraints can be extracted from a given system specification. These constraints form the basis to derive the placement of the reconfigurable areas in an automatic fashion.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127480987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783043
Y. Lechuga, R. Mozuelos, Mar Martínez, S. Bracho
This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.
{"title":"Design-for-Test method for high-speed ADCs: Behavioral description and optimization","authors":"Y. Lechuga, R. Mozuelos, Mar Martínez, S. Bracho","doi":"10.1109/DDECS.2011.5783043","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783043","url":null,"abstract":"This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114854927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783040
Muhammad Umair Ahmed Khan, H. Kerkhoff
The long-term functionality of any electronic system poses some requirements on the dependability of that system. Especially for critical systems it is becoming a crucial property with increasing system complexity and shrinking technology dimensions. Analog and mixed-signal systems are an important part of these critical systems. Until now little effort has been put into dependability of analog and mixed-signal systems, especially front/back-ends. This paper presents a new system-level platform for enhancing and analyzing the dependability of analog and mixed-signal front-ends in SoCs. Markov analysis has been used to theoretically investigate the dependability enhancement of these analog and mixed-signal front-ends based on this platform. Simulations in VHDL-AMS have also been conducted for an example target system consisting of a temperature sensor, operational amplifier and ADC to illustrate this platform. The gain parameter of the whole system, taken as an example of potential dependability hazard, has been investigated and enhanced based on this platform. The results show that this proposed platform is effective and has the potential to investigate and enhance dependability at system level.
{"title":"A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs","authors":"Muhammad Umair Ahmed Khan, H. Kerkhoff","doi":"10.1109/DDECS.2011.5783040","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783040","url":null,"abstract":"The long-term functionality of any electronic system poses some requirements on the dependability of that system. Especially for critical systems it is becoming a crucial property with increasing system complexity and shrinking technology dimensions. Analog and mixed-signal systems are an important part of these critical systems. Until now little effort has been put into dependability of analog and mixed-signal systems, especially front/back-ends. This paper presents a new system-level platform for enhancing and analyzing the dependability of analog and mixed-signal front-ends in SoCs. Markov analysis has been used to theoretically investigate the dependability enhancement of these analog and mixed-signal front-ends based on this platform. Simulations in VHDL-AMS have also been conducted for an example target system consisting of a temperature sensor, operational amplifier and ADC to illustrate this platform. The gain parameter of the whole system, taken as an example of potential dependability hazard, has been investigated and enhanced based on this platform. The results show that this proposed platform is effective and has the potential to investigate and enhance dependability at system level.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"89 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132273315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783057
T. Xu, P. Liljeberg, H. Tenhunen
In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. The improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.
{"title":"Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip","authors":"T. Xu, P. Liljeberg, H. Tenhunen","doi":"10.1109/DDECS.2011.5783057","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783057","url":null,"abstract":"In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. The improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122038683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783113
P. Bartos, Z. Kotásek, Jan Dohnal
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.
{"title":"Decreasing test time by scan chain reorganization","authors":"P. Bartos, Z. Kotásek, Jan Dohnal","doi":"10.1109/DDECS.2011.5783113","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783113","url":null,"abstract":"In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125205555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783070
P. Pawlowski, A. Dabrowski, Piotr Skrzypek, P. Roszak, Andrzej Palejko, Tomasz Walenciak, Mateusz Mor
In this paper, a complete architecture of the software defined radio receiver is proposed. First, a precise definition and the discussion of the problem is given. Next, an outline of the system topology is proposed, together with the requirements for each component of the system. Finally, a custom implementation is presented, including specifications, design considerations, and simulations.
{"title":"Software defined radio - design and implementation of complete platform","authors":"P. Pawlowski, A. Dabrowski, Piotr Skrzypek, P. Roszak, Andrzej Palejko, Tomasz Walenciak, Mateusz Mor","doi":"10.1109/DDECS.2011.5783070","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783070","url":null,"abstract":"In this paper, a complete architecture of the software defined radio receiver is proposed. First, a precise definition and the discussion of the problem is given. Next, an outline of the system topology is proposed, together with the requirements for each component of the system. Finally, a custom implementation is presented, including specifications, design considerations, and simulations.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121522939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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