Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270848
J. Rowlette, T. Eiles
A scalable laser-based timing analysis technique we call laser assisted device alteration (LADA) is introduced for the rapid isolation and analysis of defect-free performance limiting circuits in advanced flip-chip packaged microprocessors and other complex IC’s. The technique, which has been demonstrated to be widely applicable to production level as well as motherboardhystem level testing, uses a laser incident f iom the backside to perturb the timing of internal nodes by means of temporary alteration of transistor characteristics primarily by means of localized photocurrent injection. The relevant physics describing the effects of near-IR laser sources on modern day CMOS FET devices and circuits is discussed in this paper in the context of achieving precision picosecondscale timing adjustment. A selected case study where this technique was used to isolate a critical path circuit in a leading edge 130 nm generation product is provided. Scaling trends for LADA and other relevant issues are discussed.
{"title":"Critical timing analysis in microprocessors using near-ir laser assisted device alteration (lada)","authors":"J. Rowlette, T. Eiles","doi":"10.1109/TEST.2003.1270848","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270848","url":null,"abstract":"A scalable laser-based timing analysis technique we call laser assisted device alteration (LADA) is introduced for the rapid isolation and analysis of defect-free performance limiting circuits in advanced flip-chip packaged microprocessors and other complex IC’s. The technique, which has been demonstrated to be widely applicable to production level as well as motherboardhystem level testing, uses a laser incident f iom the backside to perturb the timing of internal nodes by means of temporary alteration of transistor characteristics primarily by means of localized photocurrent injection. The relevant physics describing the effects of near-IR laser sources on modern day CMOS FET devices and circuits is discussed in this paper in the context of achieving precision picosecondscale timing adjustment. A selected case study where this technique was used to isolate a critical path circuit in a leading edge 130 nm generation product is provided. Scaling trends for LADA and other relevant issues are discussed.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125563539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270844
S. Sunter
As the sampling frequency of new ADCs and DACs increases, it gets more dificult to accurately convey the analog stimulus or response to or from the converter under test - there is a bandwidth bottleneck. This paper describes a technique that uses a 400 kHz analog bus, such as the standard 1149.4 bus, to convey an arbitrary analog signal, and converts the signal to or from a high frequency at the converter, on-chip. This permits existing low-frequency distortion tests, both ATEbased and embedded, to be used for high frequency converters. High frequency noise is easily filtered out, permitting a more repeatable test and the use of low cost testers. A hypothetical 100 MHz, 14-bit ADC and DAC are used as examples. The technique has reduced sensitivity to sampling jitter, and 16-18 bit linearity appears feasible.
{"title":"Testing high frequency adcs and dacs with a low frequency analog bus","authors":"S. Sunter","doi":"10.1109/TEST.2003.1270844","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270844","url":null,"abstract":"As the sampling frequency of new ADCs and DACs increases, it gets more dificult to accurately convey the analog stimulus or response to or from the converter under test - there is a bandwidth bottleneck. This paper describes a technique that uses a 400 kHz analog bus, such as the standard 1149.4 bus, to convey an arbitrary analog signal, and converts the signal to or from a high frequency at the converter, on-chip. This permits existing low-frequency distortion tests, both ATEbased and embedded, to be used for high frequency converters. High frequency noise is easily filtered out, permitting a more repeatable test and the use of low cost testers. A hypothetical 100 MHz, 14-bit ADC and DAC are used as examples. The technique has reduced sensitivity to sampling jitter, and 16-18 bit linearity appears feasible.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271202
L. van de Logt, F. van der Heyden, T. Waayers
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to check signals. Access to these pins is becoming more difficult due to packages like BGA. The JTAG port is an efficient mechanism to gain more access to the ICs. A method is presented to reconfigure the boundary scan chain to any desired length and to access pins involved in the debugging. The method is used asynchronously or synchronously to the test clock. In asynchronous mode high transfer frequencies are possible. For synchronous mode two different variants are described where the data throughput is determined by the intermediate logic. Both modes have proven to work on an FPGA and all implementations fully retain compliancy to the IEEE 1149.1 standard.
{"title":"An extension to JTAG for at-speed debug on a system","authors":"L. van de Logt, F. van der Heyden, T. Waayers","doi":"10.1109/TEST.2003.1271202","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271202","url":null,"abstract":"When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to check signals. Access to these pins is becoming more difficult due to packages like BGA. The JTAG port is an efficient mechanism to gain more access to the ICs. A method is presented to reconfigure the boundary scan chain to any desired length and to access pins involved in the debugging. The method is used asynchronously or synchronously to the test clock. In asynchronous mode high transfer frequencies are possible. For synchronous mode two different variants are described where the data throughput is determined by the intermediate logic. Both modes have proven to work on an FPGA and all implementations fully retain compliancy to the IEEE 1149.1 standard.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122323859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271139
Johnathan Roberts
The growing test outsourcing business is characterized by a number of challenges. Production loading is nonlinear primarily due to market conditions, but also due to yield and wafer availability. This creates periods of high demand where there is a shortage of capacity and operations cycle times increase, or limited loading where the Subcontract Manufacturer (SCM) has difficulty maintaining profitability. Test operations are faced with a myriad of test requirements--from supporting multiple customers and products, maintaining and operating numerous types of testers, handlers and probers, as well as managing different tester configuration requirements based on product test needs, test strategy or simply load board layout. When test setup is protracted due to long test program load times, calibration, correlation or retest, the SCM’s effective loading decreases and cycle time increases. Moreover, all this activity must be managed within an environment of constant price pressure from the market and effective capital cost growth.
{"title":"Test outsourcing - a subcontract manufacturer's perspective","authors":"Johnathan Roberts","doi":"10.1109/TEST.2003.1271139","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271139","url":null,"abstract":"The growing test outsourcing business is characterized by a number of challenges. Production loading is nonlinear primarily due to market conditions, but also due to yield and wafer availability. This creates periods of high demand where there is a shortage of capacity and operations cycle times increase, or limited loading where the Subcontract Manufacturer (SCM) has difficulty maintaining profitability. Test operations are faced with a myriad of test requirements--from supporting multiple customers and products, maintaining and operating numerous types of testers, handlers and probers, as well as managing different tester configuration requirements based on product test needs, test strategy or simply load board layout. When test setup is protracted due to long test program load times, calibration, correlation or retest, the SCM’s effective loading decreases and cycle time increases. Moreover, all this activity must be managed within an environment of constant price pressure from the market and effective capital cost growth.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122674667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271142
F. Muradali
When test is done right, that is to an acceptable quality specification (and without impeding productivity and cost), defective parts fail the screening process. Without splitting hairs on definition, diagnosis and debug digs deeper to determine why the part is unacceptable. Troubleshooting how and why a part (or system) fails is important. For example, this may be needed for yield improvement, process monitoring, debugging the design function, failure mode learning for R&D, or just getting a working first prototype. But the detective work can become tricky. One reason for this is that, while many segments of the product creation flow (e.g. the design and test development flows) have benefited from years of study and automation, diagnosis has somewhat lagged in the formalization of techniques. Also, the test floor equipment have been traditionally designed and operated for pass/fail oriented testing. Unless this situation improves, an effective diagnosis-friendly environment may be elusive when it is needed most.
{"title":"Diagnosis in modem design - just the tip of the iceberg","authors":"F. Muradali","doi":"10.1109/TEST.2003.1271142","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271142","url":null,"abstract":"When test is done right, that is to an acceptable quality specification (and without impeding productivity and cost), defective parts fail the screening process. Without splitting hairs on definition, diagnosis and debug digs deeper to determine why the part is unacceptable. Troubleshooting how and why a part (or system) fails is important. For example, this may be needed for yield improvement, process monitoring, debugging the design function, failure mode learning for R&D, or just getting a working first prototype. But the detective work can become tricky. One reason for this is that, while many segments of the product creation flow (e.g. the design and test development flows) have benefited from years of study and automation, diagnosis has somewhat lagged in the formalization of techniques. Also, the test floor equipment have been traditionally designed and operated for pass/fail oriented testing. Unless this situation improves, an effective diagnosis-friendly environment may be elusive when it is needed most.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128243661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271095
H. Vranken, F. Hapke, Soenke Rogge, D. Chindamo, Erik H. Volkerink
paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of pre- sent ATE to assign groups of input pins to ports and to perform vector repeat per port. This allows run-length encoding of test stimuli per port. We improve the encoding byjlling the don't-care bits in the test stimuli, such that longer run-lengths are obtained. We provide a probabilis- tic analysis of the performance of vector repeat per port with various ATPG padding types. We further discuss the impact of ATE architectures. The paper provides experi- mental data for a set of large industrial circuits, which shows an average reduction of the test stimulus data vol- ume by a factor of 13.
{"title":"Atpg padding and ate vector repeat per port for reducing test data volume","authors":"H. Vranken, F. Hapke, Soenke Rogge, D. Chindamo, Erik H. Volkerink","doi":"10.1109/TEST.2003.1271095","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271095","url":null,"abstract":"paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of pre- sent ATE to assign groups of input pins to ports and to perform vector repeat per port. This allows run-length encoding of test stimuli per port. We improve the encoding byjlling the don't-care bits in the test stimuli, such that longer run-lengths are obtained. We provide a probabilis- tic analysis of the performance of vector repeat per port with various ATPG padding types. We further discuss the impact of ATE architectures. The paper provides experi- mental data for a set of large industrial circuits, which shows an average reduction of the test stimulus data vol- ume by a factor of 13.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114538999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271149
Mike P. Li
2.28 1.14 0.57
2.28 1.14 0.57
{"title":"Requirements, challenges, and solutions for testing multiple gb/s ics in production","authors":"Mike P. Li","doi":"10.1109/TEST.2003.1271149","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271149","url":null,"abstract":"2.28 1.14 0.57","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114773121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271097
K. Chung, S. Gupta
High-speed circuits use latch-based pipelines in some of their most delay-criticalparts. The use of latches not only allows attainment of high clock rate but also enables attainment of high yield at desired clock rate by permitting unintentional time borrowing. In this paper, we first demonstrate that none of the existing design-for-testability (OFT) techniques can be used to simplijj delay testing of such circuits. We then demonstrate that this leads to very high test generation and test application times. In many circuits, very low path delay fault coverage is obtained. We then propose a systematic test approach and associated DFT that significantly reduces the test generation and test application costs, and, for many circuits, significantly increases path delay fault coverage.
{"title":"Structural delay testing of latch-based high-speed pipelines with time borrowing","authors":"K. Chung, S. Gupta","doi":"10.1109/TEST.2003.1271097","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271097","url":null,"abstract":"High-speed circuits use latch-based pipelines in some of their most delay-criticalparts. The use of latches not only allows attainment of high clock rate but also enables attainment of high yield at desired clock rate by permitting unintentional time borrowing. In this paper, we first demonstrate that none of the existing design-for-testability (OFT) techniques can be used to simplijj delay testing of such circuits. We then demonstrate that this leads to very high test generation and test application times. In many circuits, very low path delay fault coverage is obtained. We then propose a systematic test approach and associated DFT that significantly reduces the test generation and test application costs, and, for many circuits, significantly increases path delay fault coverage.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127615912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270830
Haihua Yan, A. Singh
This paper presents experimental results from circuits specially implemented to evaluate a new technique for detecting delay faults in scan based designs. The faults are detected by observing circuit outputs at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. For this study a simple datapath circuit was designed and fabricated through MOSIS. Extra capacitive delays were deliberately introduced in a copy of the design. The test results presented here clearly establish the signGCant potential of the proposed new delay testing approach.
{"title":"Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die","authors":"Haihua Yan, A. Singh","doi":"10.1109/TEST.2003.1270830","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270830","url":null,"abstract":"This paper presents experimental results from circuits specially implemented to evaluate a new technique for detecting delay faults in scan based designs. The faults are detected by observing circuit outputs at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. For this study a simple datapath circuit was designed and fabricated through MOSIS. Extra capacitive delays were deliberately introduced in a copy of the design. The test results presented here clearly establish the signGCant potential of the proposed new delay testing approach.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126393720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271138
D. L. Wheater
Does one do the “minimum” DFT just to avoid buying the “next” tester, does one do all the test “on chip” and cost reduce the ATE down to a battery and a data source and sink, or is silicon so precious that any use for non mission related function make the cost of the final die prohibitive. One can easily find proponents for each position and the data to back it up. This is because the answer is highly dependent on the particulars of the design of the device and the issues related to the business case that the device is going into.
{"title":"Ate-customer perspectives & requirements panel","authors":"D. L. Wheater","doi":"10.1109/TEST.2003.1271138","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271138","url":null,"abstract":"Does one do the “minimum” DFT just to avoid buying the “next” tester, does one do all the test “on chip” and cost reduce the ATE down to a battery and a data source and sink, or is silicon so precious that any use for non mission related function make the cost of the final die prohibitive. One can easily find proponents for each position and the data to back it up. This is because the answer is highly dependent on the particulars of the design of the device and the issues related to the business case that the device is going into.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121837281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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