Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270903
R. Tekumalla
Diagnosing failing vectors in a Built-Zn Self Test (BZST) environment is a dificult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the first cycle at which incorrect responses were captured in the scan chains along with the scan cells that captured the incorrect responses. We define a diagnosis methodology that describes a simple way of diagnosing one chain at a time and jLrther shows that accurate diagnosis is possible with the aliasing nature of the MISR having no impact on diagnosis. The proposed technique results in identibing the failing vectors along with the mismatching scan cells. After determining the failing vectors and mismatching scan cells, we extend the method to identifj, potential faults in the circuit that may have resulted in the scan cells capturing incorrect responses. The method presented in this paper can be applied to diagnose multiple failing vectors also.
{"title":"On reducing aliasing effects and improving diagnosis of logic bist failures","authors":"R. Tekumalla","doi":"10.1109/TEST.2003.1270903","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270903","url":null,"abstract":"Diagnosing failing vectors in a Built-Zn Self Test (BZST) environment is a dificult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the first cycle at which incorrect responses were captured in the scan chains along with the scan cells that captured the incorrect responses. We define a diagnosis methodology that describes a simple way of diagnosing one chain at a time and jLrther shows that accurate diagnosis is possible with the aliasing nature of the MISR having no impact on diagnosis. The proposed technique results in identibing the failing vectors along with the mismatching scan cells. After determining the failing vectors and mismatching scan cells, we extend the method to identifj, potential faults in the circuit that may have resulted in the scan cells capturing incorrect responses. The method presented in this paper can be applied to diagnose multiple failing vectors also.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127207861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271120
A. Singh
Escapes from manufacturing test: A large system built out of well-tested components can still have a significant probability of failure due to test escapes. Unfortunately field testing is unlikely to detect such failures because manufacturing tests, carried out on individual parts and on assembled (sub)systems, are far more comprehensive. Indeed, any proposed field test can be applied as part of manufacturing tests, but reapplying all manufacturing tests is generally not possible in the field. Thus it is unrealistic to expect a significant number of manufacturing test escapes to be picked up by subsequent field-testing, unless the defects “grow” in the field and cause additional malfunction. Concurrent test methods, such as self checking, on the other hand, can be effective here since they can detect errors for input conditions not observed during test.
{"title":"Should nanometer circuits be periodically tested in the field?","authors":"A. Singh","doi":"10.1109/TEST.2003.1271120","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271120","url":null,"abstract":"Escapes from manufacturing test: A large system built out of well-tested components can still have a significant probability of failure due to test escapes. Unfortunately field testing is unlikely to detect such failures because manufacturing tests, carried out on individual parts and on assembled (sub)systems, are far more comprehensive. Indeed, any proposed field test can be applied as part of manufacturing tests, but reapplying all manufacturing tests is generally not possible in the field. Thus it is unrealistic to expect a significant number of manufacturing test escapes to be picked up by subsequent field-testing, unless the defects “grow” in the field and cause additional malfunction. Concurrent test methods, such as self checking, on the other hand, can be effective here since they can detect errors for input conditions not observed during test.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130943741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270865
Nobuhiro Sato, Y. Hashimoto
This paper describes a system for performing high precision IDDQ measurement of CMOS ICs having a large peak current during operation. Although the measurement rate is at a low speed of 200uS, the average current of up to 1A during operation may be accepted by improving the dynamic load regulation. This system is also applicable to conventional testing apparatus. This paper covers problems in IDDQ testing, solution for the problems, embodiment of each circuit, verijication of the results, conclusion and future issues.
{"title":"A high precision iddq measurement system with improved dynamic load regulation","authors":"Nobuhiro Sato, Y. Hashimoto","doi":"10.1109/TEST.2003.1270865","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270865","url":null,"abstract":"This paper describes a system for performing high precision IDDQ measurement of CMOS ICs having a large peak current during operation. Although the measurement rate is at a low speed of 200uS, the average current of up to 1A during operation may be accepted by improving the dynamic load regulation. This system is also applicable to conventional testing apparatus. This paper covers problems in IDDQ testing, solution for the problems, embodiment of each circuit, verijication of the results, conclusion and future issues.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130407884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271117
W. Rijckaert, F. Jong
Test coverage prediction for board-assemblies has an important function in, among others, test engineering, test cost modeling, test strategy definition and product quality estimation. Introducing a method that defines how this coverage is calculated can increase the value of such prediction across the electronics industry. We consider the three aspects to test coverage calculation: fault modeling, coverage per fault and total coverage. An abstraction level for fault categories is introduced, called MPS (material, placement, soldering) that enables us to compare coverage results using different fault models. Additionally, the rule based fault coverage estimation and the weighted coverage calculation are discussed.
{"title":"Board test coverage: the value of prediction and how to compare numbers","authors":"W. Rijckaert, F. Jong","doi":"10.1109/TEST.2003.1271117","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271117","url":null,"abstract":"Test coverage prediction for board-assemblies has an important function in, among others, test engineering, test cost modeling, test strategy definition and product quality estimation. Introducing a method that defines how this coverage is calculated can increase the value of such prediction across the electronics industry. We consider the three aspects to test coverage calculation: fault modeling, coverage per fault and total coverage. An abstraction level for fault categories is introduced, called MPS (material, placement, soldering) that enables us to compare coverage results using different fault models. Additionally, the rule based fault coverage estimation and the weighted coverage calculation are discussed.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126364740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270853
T. Vogels, Wojciech Maly, R. D. Blanton
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wiredAND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results.
{"title":"Progressive bridge identification","authors":"T. Vogels, Wojciech Maly, R. D. Blanton","doi":"10.1109/TEST.2003.1270853","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270853","url":null,"abstract":"We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wiredAND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121553824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271101
L. Forli, J. Portal, D. Née, B. Borot
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a bottom-up approach with emphasis on its scalability. Using this infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be quickly and easily performed. To reach this goal, the test flow and its related signature extraction is given. Thus, the use of this I-IP allows to improve the manufacturing process by diagnosing the back-end yield loss.
{"title":"Infrastructure IP for back-end yield improvement","authors":"L. Forli, J. Portal, D. Née, B. Borot","doi":"10.1109/TEST.2003.1271101","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271101","url":null,"abstract":"The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a bottom-up approach with emphasis on its scalability. Using this infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be quickly and easily performed. To reach this goal, the test flow and its related signature extraction is given. Thus, the use of this I-IP allows to improve the manufacturing process by diagnosing the back-end yield loss.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126818800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271102
E. Larsson, Zebo Peng
This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.
{"title":"A reconfigurable power-conscious core wrapper and its application to soc test scheduling","authors":"E. Larsson, Zebo Peng","doi":"10.1109/TEST.2003.1271102","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271102","url":null,"abstract":"This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"34 50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116216178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271132
P. Varma
Recently, assertion based verification or property checking has become of great interest to the industry. Property checkers attempt either to prove that a specified property, which stipulates expected design behavior, holds or, if the property does not hold, to generate a counter-example that demonstrates a violation of the property. This is another area where there have been some promising successes in recent years, with sequential ATPG techniques finding their way into commercial property checking tools.
{"title":"Design verification problems: test to the rescue?","authors":"P. Varma","doi":"10.1109/TEST.2003.1271132","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271132","url":null,"abstract":"Recently, assertion based verification or property checking has become of great interest to the industry. Property checkers attempt either to prove that a specified property, which stipulates expected design behavior, holds or, if the property does not hold, to generate a counter-example that demonstrates a violation of the property. This is another area where there have been some promising successes in recent years, with sequential ATPG techniques finding their way into commercial property checking tools.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"73 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114006008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271073
R. D. Blanton, K. N. Dwarakanath, A. Shah
Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.
{"title":"Analyzing the effectiveness of multiple-detect test sets","authors":"R. D. Blanton, K. N. Dwarakanath, A. Shah","doi":"10.1109/TEST.2003.1271073","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271073","url":null,"abstract":"Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270825
Takahiro J. Yamaguchi, M. Soma, M. Ishida, M. Kurosawa, H. Musha
This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new jitter tolerance model is verified with experimental data on cables of various lengths, using both PRBS and T11 test patterns.
{"title":"Effects of deterministic jitter in a cable on jitter tolerance measurements","authors":"Takahiro J. Yamaguchi, M. Soma, M. Ishida, M. Kurosawa, H. Musha","doi":"10.1109/TEST.2003.1270825","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270825","url":null,"abstract":"This paper presents a new jitter tolerance model that includes the effect of deterministic jitter in interconnects. First, it is shown by experiment that the deterministic jitter in a cable can significantly affect its jitter tolerance. Then, the new jitter tolerance model is verified with experimental data on cables of various lengths, using both PRBS and T11 test patterns.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132542393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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