Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271121
P. Nigh
It is becoming more challenging to achieve very high reliability for products made with advanced technologies (90nm and smaller). [International Technology Semiconductor Roadmap, 20021 There are a variety of reasons for this trend--a brief summary is included below. This trend will force IC manufacturers to adopt new test and stress methods and to improve product reliability using system architecture enhancements-including the use of extensive on-line testing. ln this summary paper, I will describe the key problems driving this change and describe some of the methods that can be used to improve final product reliability. I believe that many of the same methods used to improve testing at the chip and package can be used to improve reliability at the system level. In fact, if such methods are not used there is likelihood that products may become less reliable over time-which is not acceptable to many applications. The issues that make it more difficult to screen all defects during wafer or package-level testing include: There is an increase in subtle, hard-to-detect defects for advanced technologies. Such defects include resistive vias, resistive shorts and implant deformations. These defect types may cause only minor performance abnormalities that are very difficult to exhaustively detect using state-of-the-art test methods. Such defects may cause only a few picoseconds of delay, for example. Subtle defects (such as resistive vias) may degrade with use and are not stressed well by conventional methods (relying on voltage and temperature acceleration) such as burn-in. These defects may only be accelerated by current density changes requiring many cycles of applying various circuit states to the device. Difficulty in stressing these defects will drive manufacturers to improve their test methods-nabling these defects to be detected rather than accelerated. The effectiveness of stress methods for reliabilitytype defects is degrading. For example, the difference in voltage between the application and high-voltage stress testing is decreasing for advanced technologies causing an exponential decrease in stress effectiveness. Burn-in stressing is becoming problematic due to very high leakage currents at burn-in. IDDQ testing is becoming less effective due to increasing leakage currents. The margin between the application condition and where the device actually operates is eroding. For 0.18um products, there was open I Volt of margin between the design target VDD voltage and the minimum functional VDD at test (at slower conditions). For 90nm, this margin may shrink to less than 200mV. Many applications will have reduced margins for other parameters than VDD voltage (such as temperature & speed) which may lead to more intermittent failures. Reliability-type failures may soon be caused by “expected” performance degradations such as Negative Bias Temperature Instability (NBTI). Given these expected degradations, IC suppliers must decide how to account for dev
{"title":"The increasing importance of on-line testing to ensure high-reliability products","authors":"P. Nigh","doi":"10.1109/TEST.2003.1271121","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271121","url":null,"abstract":"It is becoming more challenging to achieve very high reliability for products made with advanced technologies (90nm and smaller). [International Technology Semiconductor Roadmap, 20021 There are a variety of reasons for this trend--a brief summary is included below. This trend will force IC manufacturers to adopt new test and stress methods and to improve product reliability using system architecture enhancements-including the use of extensive on-line testing. ln this summary paper, I will describe the key problems driving this change and describe some of the methods that can be used to improve final product reliability. I believe that many of the same methods used to improve testing at the chip and package can be used to improve reliability at the system level. In fact, if such methods are not used there is likelihood that products may become less reliable over time-which is not acceptable to many applications. The issues that make it more difficult to screen all defects during wafer or package-level testing include: There is an increase in subtle, hard-to-detect defects for advanced technologies. Such defects include resistive vias, resistive shorts and implant deformations. These defect types may cause only minor performance abnormalities that are very difficult to exhaustively detect using state-of-the-art test methods. Such defects may cause only a few picoseconds of delay, for example. Subtle defects (such as resistive vias) may degrade with use and are not stressed well by conventional methods (relying on voltage and temperature acceleration) such as burn-in. These defects may only be accelerated by current density changes requiring many cycles of applying various circuit states to the device. Difficulty in stressing these defects will drive manufacturers to improve their test methods-nabling these defects to be detected rather than accelerated. The effectiveness of stress methods for reliabilitytype defects is degrading. For example, the difference in voltage between the application and high-voltage stress testing is decreasing for advanced technologies causing an exponential decrease in stress effectiveness. Burn-in stressing is becoming problematic due to very high leakage currents at burn-in. IDDQ testing is becoming less effective due to increasing leakage currents. The margin between the application condition and where the device actually operates is eroding. For 0.18um products, there was open I Volt of margin between the design target VDD voltage and the minimum functional VDD at test (at slower conditions). For 90nm, this margin may shrink to less than 200mV. Many applications will have reduced margins for other parameters than VDD voltage (such as temperature & speed) which may lead to more intermittent failures. Reliability-type failures may soon be caused by “expected” performance degradations such as Negative Bias Temperature Instability (NBTI). Given these expected degradations, IC suppliers must decide how to account for dev","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132795936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271092
Li-C. Wang, Angela Krstic, Leonard Lee, K. Cheng, M. R. Mercer, T. Williams, M. Abadir
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic models: the Williams-Brown (WB) model and the Mercer-Park-GrimailaDworak (MPGD) model. In the WB-model, the defect coverage is replaced by the n-detection transition fault coverage. We first demonstrate that both logic models may fail to predict the detection of statistical timing defects. Then, we propose an improved WB model based upon selection of the hard-to-detect transition faults. We show that, by selecting a proper subset of the hard-to-detect transition faults, the detection behavior of these faults can correlate well to the detection behavior of statistical timing defects. We explain our findings through statistical delay defect injection and simulation, and report results based upon various benchmark circuits.
本文研究了利用逻辑缺陷级预测模型来预测统计时序缺陷检测行为的可能性。我们比较了两种已知的逻辑模型:Williams-Brown (WB)模型和mercer - park - grimailadwork (MPGD)模型。在wb模型中，缺陷覆盖被n检测转换故障覆盖所取代。我们首先证明了这两种逻辑模型可能无法预测统计时序缺陷的检测。然后，我们提出了一种基于难以检测的过渡故障选择的改进WB模型。研究表明，通过选择难以检测的过渡故障的适当子集，这些故障的检测行为可以很好地与统计时序缺陷的检测行为相关联。我们通过统计延迟缺陷注入和模拟来解释我们的发现，并报告基于各种基准电路的结果。
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Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271144
W. Huott
The pain of debug, from 1 silicon to volume ramp Debug, especially in custom chip design (i.e.: microprocessors), many times seems to be more of a reactionary “fly by the seat of your pants” art than a “well thought out” tools-based procedure to solution. In fact, it is quite difficult to define tools to do 1 silicon debug since it seems each new problem is somehow specifically associated to some particular design facet or interaction of that facet with the particular silicon process you’re operating in.
{"title":"Diagnosis in modem design to volume the tip of the iceberg","authors":"W. Huott","doi":"10.1109/TEST.2003.1271144","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271144","url":null,"abstract":"The pain of debug, from 1 silicon to volume ramp Debug, especially in custom chip design (i.e.: microprocessors), many times seems to be more of a reactionary “fly by the seat of your pants” art than a “well thought out” tools-based procedure to solution. In fact, it is quite difficult to define tools to do 1 silicon debug since it seems each new problem is somehow specifically associated to some particular design facet or interaction of that facet with the particular silicon process you’re operating in.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270828
Y. Nishizaki, O. Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura
This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.
{"title":"Testing DSM asic with static, /spl delta/IDDQ, and dynamic test suite: implementation and results","authors":"Y. Nishizaki, O. Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura","doi":"10.1109/TEST.2003.1270828","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270828","url":null,"abstract":"This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"38 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271071
Wojciech Maly, A. Gattiker, T. Zanon, T. Vogels, R. D. Blanton, T. Storey
Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.
{"title":"Deformations of ic structure in test and yield learning","authors":"Wojciech Maly, A. Gattiker, T. Zanon, T. Vogels, R. D. Blanton, T. Storey","doi":"10.1109/TEST.2003.1271071","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271071","url":null,"abstract":"Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271220
T. Piironen
DSP processing power of the product itself is used more and more to replace external measurement and test instruments leading to lower investment costs at manufacturing. This is affecting greatly on test strategies used in product development. Design for Testing (DFT) has to be considered in very early design phases and consists integral part of the later design and implementation phases, too. In addition to production the whole life-cycle of the product, including field use, service and maintenance has also been integrated into test strategies. This is emphasizing the importance of selfdiagnostics functions of the product. As a result the management of test integration in R&D has become a critical success factor.
{"title":"Board life-cycle testing for effective npi management of wireless products","authors":"T. Piironen","doi":"10.1109/TEST.2003.1271220","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271220","url":null,"abstract":"DSP processing power of the product itself is used more and more to replace external measurement and test instruments leading to lower investment costs at manufacturing. This is affecting greatly on test strategies used in product development. Design for Testing (DFT) has to be considered in very early design phases and consists integral part of the later design and implementation phases, too. In addition to production the whole life-cycle of the product, including field use, service and maintenance has also been integrated into test strategies. This is emphasizing the importance of selfdiagnostics functions of the product. As a result the management of test integration in R&D has become a critical success factor.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270880
T. P. Warwick
This paper discusses the issues associated causing jitter in the measurement path can be well with removing the effects of the measurement path characterized and simulated, simple methods of in very high speed measurements. Of critical compensating for measurement path error cannot be concern is deterministic jitter caused by the applied. This paper explores this issue and suggests interaction between the measurement path and the two complementary solutions for addressing such device under test. While individual components jitter.
{"title":"Mitigating the effects of the dut interface board and test system parasitics in gigabit-plus measurements","authors":"T. P. Warwick","doi":"10.1109/TEST.2003.1270880","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270880","url":null,"abstract":"This paper discusses the issues associated causing jitter in the measurement path can be well with removing the effects of the measurement path characterized and simulated, simple methods of in very high speed measurements. Of critical compensating for measurement path error cannot be concern is deterministic jitter caused by the applied. This paper explores this issue and suggests interaction between the measurement path and the two complementary solutions for addressing such device under test. While individual components jitter.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128294070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270832
R. Kundu, R. D. Blanton
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.
{"title":"Path delay test generation for domino logic circuits in the presence of crosstalk","authors":"R. Kundu, R. D. Blanton","doi":"10.1109/TEST.2003.1270832","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270832","url":null,"abstract":"A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"66 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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