Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271121
P. Nigh
It is becoming more challenging to achieve very high reliability for products made with advanced technologies (90nm and smaller). [International Technology Semiconductor Roadmap, 20021 There are a variety of reasons for this trend--a brief summary is included below. This trend will force IC manufacturers to adopt new test and stress methods and to improve product reliability using system architecture enhancements-including the use of extensive on-line testing. ln this summary paper, I will describe the key problems driving this change and describe some of the methods that can be used to improve final product reliability. I believe that many of the same methods used to improve testing at the chip and package can be used to improve reliability at the system level. In fact, if such methods are not used there is likelihood that products may become less reliable over time-which is not acceptable to many applications. The issues that make it more difficult to screen all defects during wafer or package-level testing include: There is an increase in subtle, hard-to-detect defects for advanced technologies. Such defects include resistive vias, resistive shorts and implant deformations. These defect types may cause only minor performance abnormalities that are very difficult to exhaustively detect using state-of-the-art test methods. Such defects may cause only a few picoseconds of delay, for example. Subtle defects (such as resistive vias) may degrade with use and are not stressed well by conventional methods (relying on voltage and temperature acceleration) such as burn-in. These defects may only be accelerated by current density changes requiring many cycles of applying various circuit states to the device. Difficulty in stressing these defects will drive manufacturers to improve their test methods-nabling these defects to be detected rather than accelerated. The effectiveness of stress methods for reliabilitytype defects is degrading. For example, the difference in voltage between the application and high-voltage stress testing is decreasing for advanced technologies causing an exponential decrease in stress effectiveness. Burn-in stressing is becoming problematic due to very high leakage currents at burn-in. IDDQ testing is becoming less effective due to increasing leakage currents. The margin between the application condition and where the device actually operates is eroding. For 0.18um products, there was open I Volt of margin between the design target VDD voltage and the minimum functional VDD at test (at slower conditions). For 90nm, this margin may shrink to less than 200mV. Many applications will have reduced margins for other parameters than VDD voltage (such as temperature & speed) which may lead to more intermittent failures. Reliability-type failures may soon be caused by “expected” performance degradations such as Negative Bias Temperature Instability (NBTI). Given these expected degradations, IC suppliers must decide how to account for dev
{"title":"The increasing importance of on-line testing to ensure high-reliability products","authors":"P. Nigh","doi":"10.1109/TEST.2003.1271121","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271121","url":null,"abstract":"It is becoming more challenging to achieve very high reliability for products made with advanced technologies (90nm and smaller). [International Technology Semiconductor Roadmap, 20021 There are a variety of reasons for this trend--a brief summary is included below. This trend will force IC manufacturers to adopt new test and stress methods and to improve product reliability using system architecture enhancements-including the use of extensive on-line testing. ln this summary paper, I will describe the key problems driving this change and describe some of the methods that can be used to improve final product reliability. I believe that many of the same methods used to improve testing at the chip and package can be used to improve reliability at the system level. In fact, if such methods are not used there is likelihood that products may become less reliable over time-which is not acceptable to many applications. The issues that make it more difficult to screen all defects during wafer or package-level testing include: There is an increase in subtle, hard-to-detect defects for advanced technologies. Such defects include resistive vias, resistive shorts and implant deformations. These defect types may cause only minor performance abnormalities that are very difficult to exhaustively detect using state-of-the-art test methods. Such defects may cause only a few picoseconds of delay, for example. Subtle defects (such as resistive vias) may degrade with use and are not stressed well by conventional methods (relying on voltage and temperature acceleration) such as burn-in. These defects may only be accelerated by current density changes requiring many cycles of applying various circuit states to the device. Difficulty in stressing these defects will drive manufacturers to improve their test methods-nabling these defects to be detected rather than accelerated. The effectiveness of stress methods for reliabilitytype defects is degrading. For example, the difference in voltage between the application and high-voltage stress testing is decreasing for advanced technologies causing an exponential decrease in stress effectiveness. Burn-in stressing is becoming problematic due to very high leakage currents at burn-in. IDDQ testing is becoming less effective due to increasing leakage currents. The margin between the application condition and where the device actually operates is eroding. For 0.18um products, there was open I Volt of margin between the design target VDD voltage and the minimum functional VDD at test (at slower conditions). For 90nm, this margin may shrink to less than 200mV. Many applications will have reduced margins for other parameters than VDD voltage (such as temperature & speed) which may lead to more intermittent failures. Reliability-type failures may soon be caused by “expected” performance degradations such as Negative Bias Temperature Instability (NBTI). Given these expected degradations, IC suppliers must decide how to account for dev","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132795936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271092
Li-C. Wang, Angela Krstic, Leonard Lee, K. Cheng, M. R. Mercer, T. Williams, M. Abadir
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic models: the Williams-Brown (WB) model and the Mercer-Park-GrimailaDworak (MPGD) model. In the WB-model, the defect coverage is replaced by the n-detection transition fault coverage. We first demonstrate that both logic models may fail to predict the detection of statistical timing defects. Then, we propose an improved WB model based upon selection of the hard-to-detect transition faults. We show that, by selecting a proper subset of the hard-to-detect transition faults, the detection behavior of these faults can correlate well to the detection behavior of statistical timing defects. We explain our findings through statistical delay defect injection and simulation, and report results based upon various benchmark circuits.
本文研究了利用逻辑缺陷级预测模型来预测统计时序缺陷检测行为的可能性。我们比较了两种已知的逻辑模型:Williams-Brown (WB)模型和mercer - park - grimailadwork (MPGD)模型。在wb模型中，缺陷覆盖被n检测转换故障覆盖所取代。我们首先证明了这两种逻辑模型可能无法预测统计时序缺陷的检测。然后，我们提出了一种基于难以检测的过渡故障选择的改进WB模型。研究表明，通过选择难以检测的过渡故障的适当子集，这些故障的检测行为可以很好地与统计时序缺陷的检测行为相关联。我们通过统计延迟缺陷注入和模拟来解释我们的发现，并报告基于各种基准电路的结果。
{"title":"Using logic models to predict the detection behavior of statistical timing defects","authors":"Li-C. Wang, Angela Krstic, Leonard Lee, K. Cheng, M. R. Mercer, T. Williams, M. Abadir","doi":"10.1109/TEST.2003.1271092","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271092","url":null,"abstract":"In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic models: the Williams-Brown (WB) model and the Mercer-Park-GrimailaDworak (MPGD) model. In the WB-model, the defect coverage is replaced by the n-detection transition fault coverage. We first demonstrate that both logic models may fail to predict the detection of statistical timing defects. Then, we propose an improved WB model based upon selection of the hard-to-detect transition faults. We show that, by selecting a proper subset of the hard-to-detect transition faults, the detection behavior of these faults can correlate well to the detection behavior of statistical timing defects. We explain our findings through statistical delay defect injection and simulation, and report results based upon various benchmark circuits.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133276868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270845
F. Stellari, P. Song, M. McManus, R. Gauthier, A. Weger, K. Chatty, M. Muhammad, P. Sanda
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.
{"title":"Optical and electrical testing of latchup in I/O interface circuits","authors":"F. Stellari, P. Song, M. McManus, R. Gauthier, A. Weger, K. Chatty, M. Muhammad, P. Sanda","doi":"10.1109/TEST.2003.1270845","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270845","url":null,"abstract":"Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270883
C. Schuermyer, B. Benware, Kevin Cota, R. Madge, W. R. Daasch, L. Ning
Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under Test (DUT) and takes two quiescent current measurements. The quiescent current measurements are taken at nominal and at subthreshold supply voltages. The scr een is demonstrated with 0.18µm and 0.13µm volume data. The screen's effectiveness is compared to stuck -at and other IDDQ screens.
{"title":"Screening vdsm outliers using nominal and subthreshold supply voltage I/sub DDQ/","authors":"C. Schuermyer, B. Benware, Kevin Cota, R. Madge, W. R. Daasch, L. Ning","doi":"10.1109/TEST.2003.1270883","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270883","url":null,"abstract":"Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under Test (DUT) and takes two quiescent current measurements. The quiescent current measurements are taken at nominal and at subthreshold supply voltages. The scr een is demonstrated with 0.18µm and 0.13µm volume data. The screen's effectiveness is compared to stuck -at and other IDDQ screens.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133297105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270873
T. Yoshida, M. Watari
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we have found that power supply voltage drops cause testing problems during shift operations in scan testing and we have analyzed this phenomenon and its causes. In this paper, we present a new testing method named MD-SCAN (Multi Duty-Scan) which solves power supply voltage drop problems in scan testing, as well as offering an eficient method of appkcation.
{"title":"A new approach for low-power scan testing","authors":"T. Yoshida, M. Watari","doi":"10.1109/TEST.2003.1270873","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270873","url":null,"abstract":"As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we have found that power supply voltage drops cause testing problems during shift operations in scan testing and we have analyzed this phenomenon and its causes. In this paper, we present a new testing method named MD-SCAN (Multi Duty-Scan) which solves power supply voltage drop problems in scan testing, as well as offering an eficient method of appkcation.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"136 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120940887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271144
W. Huott
The pain of debug, from 1 silicon to volume ramp Debug, especially in custom chip design (i.e.: microprocessors), many times seems to be more of a reactionary “fly by the seat of your pants” art than a “well thought out” tools-based procedure to solution. In fact, it is quite difficult to define tools to do 1 silicon debug since it seems each new problem is somehow specifically associated to some particular design facet or interaction of that facet with the particular silicon process you’re operating in.
{"title":"Diagnosis in modem design to volume the tip of the iceberg","authors":"W. Huott","doi":"10.1109/TEST.2003.1271144","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271144","url":null,"abstract":"The pain of debug, from 1 silicon to volume ramp Debug, especially in custom chip design (i.e.: microprocessors), many times seems to be more of a reactionary “fly by the seat of your pants” art than a “well thought out” tools-based procedure to solution. In fact, it is quite difficult to define tools to do 1 silicon debug since it seems each new problem is somehow specifically associated to some particular design facet or interaction of that facet with the particular silicon process you’re operating in.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271071
Wojciech Maly, A. Gattiker, T. Zanon, T. Vogels, R. D. Blanton, T. Storey
Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.
{"title":"Deformations of ic structure in test and yield learning","authors":"Wojciech Maly, A. Gattiker, T. Zanon, T. Vogels, R. D. Blanton, T. Storey","doi":"10.1109/TEST.2003.1271071","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271071","url":null,"abstract":"Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270850
Qingwei Wu, M. Hsiao
We present a new automatic test pattern generation algorithm for sequential circuits by traversing the partitioned state spaces. The new features include: (1) nondisjoint state groups are obtained such that two different state groups may have common flip-flops, (2) partial state transition graphs (STGs) are constructed at run time for each state group, (3) spectral information for state variables are extracted and the spectral information of the state variables helps to identify the behavior of the flip-flops in the frequency domain. This information will help us to intelligently partition the state space. We focus only on the STGs for the flip-flops that are grouped together instead of building the STG for the entire circuit, and the ATPG tries to traverse all states and transitions within each partial STG. By exercising states visited and arcs traversed, the vectors generated often lead to the detection of hard faults. Since we limit a maximum size any state group can be, construction of partitioned STGs is feasible even for very large sequential circuits. Only logic simulation is needed in our ATPG; as a result, the execution time is greatly reduced while achieving high fault coverages compared with other test generators. For some large sequential circuits, highest fault coverages have been achieved.
{"title":"Efficient sequential atpg based on partitioned finite-state-machine traversal","authors":"Qingwei Wu, M. Hsiao","doi":"10.1109/TEST.2003.1270850","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270850","url":null,"abstract":"We present a new automatic test pattern generation algorithm for sequential circuits by traversing the partitioned state spaces. The new features include: (1) nondisjoint state groups are obtained such that two different state groups may have common flip-flops, (2) partial state transition graphs (STGs) are constructed at run time for each state group, (3) spectral information for state variables are extracted and the spectral information of the state variables helps to identify the behavior of the flip-flops in the frequency domain. This information will help us to intelligently partition the state space. We focus only on the STGs for the flip-flops that are grouped together instead of building the STG for the entire circuit, and the ATPG tries to traverse all states and transitions within each partial STG. By exercising states visited and arcs traversed, the vectors generated often lead to the detection of hard faults. Since we limit a maximum size any state group can be, construction of partitioned STGs is feasible even for very large sequential circuits. Only logic simulation is needed in our ATPG; as a result, the execution time is greatly reduced while achieving high fault coverages compared with other test generators. For some large sequential circuits, highest fault coverages have been achieved.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130363757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271220
T. Piironen
DSP processing power of the product itself is used more and more to replace external measurement and test instruments leading to lower investment costs at manufacturing. This is affecting greatly on test strategies used in product development. Design for Testing (DFT) has to be considered in very early design phases and consists integral part of the later design and implementation phases, too. In addition to production the whole life-cycle of the product, including field use, service and maintenance has also been integrated into test strategies. This is emphasizing the importance of selfdiagnostics functions of the product. As a result the management of test integration in R&D has become a critical success factor.
{"title":"Board life-cycle testing for effective npi management of wireless products","authors":"T. Piironen","doi":"10.1109/TEST.2003.1271220","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271220","url":null,"abstract":"DSP processing power of the product itself is used more and more to replace external measurement and test instruments leading to lower investment costs at manufacturing. This is affecting greatly on test strategies used in product development. Design for Testing (DFT) has to be considered in very early design phases and consists integral part of the later design and implementation phases, too. In addition to production the whole life-cycle of the product, including field use, service and maintenance has also been integrated into test strategies. This is emphasizing the importance of selfdiagnostics functions of the product. As a result the management of test integration in R&D has become a critical success factor.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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