Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270887
O. Sinanoglu, A. Orailoglu
Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scanbased cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We provide a mathematical analysis that helps model the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Even in the highly challenging case of fully specified test vectors, more than an order of magnitude reduction in scan-in power is attained by the proposed methodology, exceeding previous power reduction levels significantly.
{"title":"Modeling scan chain modifications for scan-in test power minimization","authors":"O. Sinanoglu, A. Orailoglu","doi":"10.1109/TEST.2003.1270887","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270887","url":null,"abstract":"Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scanbased cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We provide a mathematical analysis that helps model the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Even in the highly challenging case of fully specified test vectors, more than an order of magnitude reduction in scan-in power is attained by the proposed methodology, exceeding previous power reduction levels significantly.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132245281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270899
Wanli Jiang, Eric Peterson, Bob Robotka
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ECR tests may be degraded by a large number of normal transitions in a circuit, which may bury the fault impact on the overall current. For deterministic ECRs, the fault-oriented ECR tests are generated with an algorithm to minimize the number of normal transitions not related with the sensitizable path of the target faults. For generalized ECRs, however, the test patterns are generic without targeting any spec@ faults and therefore may cause a signijicant amount of transient activities in a CUT. This issue is addressed in this paper by utilizing a DFT technique, multiple scan chain design. This technique virtually partitions the circuit into several sections, so that the transitions in each section can be much less compared with those in the whole circuit. The fault impact can be more signijicant with fewer transitions in the circuit, which hence increases the ECR test effectiveness. The anti-process-variation property of the ECR metric is also demonstrated through a negligible lotto-lot shift. Finally, the effectiveness of ECR tests with different thresholds is compared with existing traditionul tests.
{"title":"Effectiveness improvement of ecr tests","authors":"Wanli Jiang, Eric Peterson, Bob Robotka","doi":"10.1109/TEST.2003.1270899","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270899","url":null,"abstract":"Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ECR tests may be degraded by a large number of normal transitions in a circuit, which may bury the fault impact on the overall current. For deterministic ECRs, the fault-oriented ECR tests are generated with an algorithm to minimize the number of normal transitions not related with the sensitizable path of the target faults. For generalized ECRs, however, the test patterns are generic without targeting any spec@ faults and therefore may cause a signijicant amount of transient activities in a CUT. This issue is addressed in this paper by utilizing a DFT technique, multiple scan chain design. This technique virtually partitions the circuit into several sections, so that the transitions in each section can be much less compared with those in the whole circuit. The fault impact can be more signijicant with fewer transitions in the circuit, which hence increases the ECR test effectiveness. The anti-process-variation property of the ECR metric is also demonstrated through a negligible lotto-lot shift. Finally, the effectiveness of ECR tests with different thresholds is compared with existing traditionul tests.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130256610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271080
Zhen Shi, P. Sandborn
This paper presents a framework for optimizing the location(s) and characteristics (fault coverage/test cost, rework success rate/rework cost) of Test/Diagnosis/Rework (TDR) operations in the assembly process for electronic systems. A new search algorithm called Waiting Sequence Search (WSS) is applied to traverse a general process flow in order to perform the cumulative calculation of a yielded cost objective function. Real-Coded Genetic Algorithms (RCGAs) are used to perform a multi-variable optimization that minimizes yielded cost. Several simple cases are analyzed for validation and a general complex process flow is used to demonstrate the applicability of the algorithm.
{"title":"Optimization of test/diagnosis/rework location(s) and characteristics in electronic systems assembly using real-coded genetic algorithms","authors":"Zhen Shi, P. Sandborn","doi":"10.1109/TEST.2003.1271080","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271080","url":null,"abstract":"This paper presents a framework for optimizing the location(s) and characteristics (fault coverage/test cost, rework success rate/rework cost) of Test/Diagnosis/Rework (TDR) operations in the assembly process for electronic systems. A new search algorithm called Waiting Sequence Search (WSS) is applied to traverse a general process flow in order to perform the cumulative calculation of a yielded cost objective function. Real-Coded Genetic Algorithms (RCGAs) are used to perform a multi-variable optimization that minimizes yielded cost. Several simple cases are analyzed for validation and a general complex process flow is used to demonstrate the applicability of the algorithm.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134060935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271127
A. Chatterjee
{"title":"Seamless research between academia and industry to facilitate test of integrated high-speed wireless systems: is this an illusion?","authors":"A. Chatterjee","doi":"10.1109/TEST.2003.1271127","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271127","url":null,"abstract":"","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133018105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270870
Armin Würtenberger, C. Tautermann, S. Hellebrand
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that run-length coding, particularly alternating run-length coding, can provide high compression ratios for the test data. However, experimental data show that longer runlengths are distributed sparsely in the code space and often occur only once, which implies an ineficient encoding. In this study a hybrid encoding strategy is presented which overcomes this problem by combining both the advantages of run-length and dictionary-based encoding. The compression ratios strongly depend on the strategy of mapping don't cares in the original test set to zeros or ones. To find the best assignment an algorithm is proposed which minimizes the total size of the test data consisting of the encoded test set and the dictionary. Experimental results show that the proposed approach works particularly well for larger examples yielding a significant reduction of the total test data storage compared to pure alternating run-length coding.
{"title":"A hybrid coding strategy for optimized test data compression","authors":"Armin Würtenberger, C. Tautermann, S. Hellebrand","doi":"10.1109/TEST.2003.1270870","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270870","url":null,"abstract":"Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that run-length coding, particularly alternating run-length coding, can provide high compression ratios for the test data. However, experimental data show that longer runlengths are distributed sparsely in the code space and often occur only once, which implies an ineficient encoding. In this study a hybrid encoding strategy is presented which overcomes this problem by combining both the advantages of run-length and dictionary-based encoding. The compression ratios strongly depend on the strategy of mapping don't cares in the original test set to zeros or ones. To find the best assignment an algorithm is proposed which minimizes the total size of the test data consisting of the encoded test set and the dictionary. Experimental results show that the proposed approach works particularly well for larger examples yielding a significant reduction of the total test data storage compared to pure alternating run-length coding.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116940089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271143
R. Molyneaux
The current scale of integration is the greatest driving force for needing better and faster, debug capabilities. We are truly building systems on a chip, board level interfaces which could previously be monitored and debugged with logic analyzers are now buried on silicon. We need to consider burying the logic analyzers along with the interfaces. The debug task is sometimes made more difficult in today’s environment with the increased reuse of internal IP, the use of externally supplied IP and remote foundries. Internal reuse of IP may not at first seem like a complicating factor but consider the likely fact that few if any of the original designers of that block are still with the company and you are intending to use it in a design that they had not even thought of. With increased IP reuse our marketing folks, in their infinite wisdom, are tempted to offer more parts in the market, many just a small customization of the base model. “Hey just cut the cache in half, slap on a 10/100 IP block from TI, cut the cost by 30% and we’ve opened up a whole new market!” Right! We are not plug and play in the microprocessor component domain yet. We are executing these design customizations but at this time the extended debug phase may more than compensate for the design time saved due to IP purchase or reuse.
{"title":"Debug and diagnosis in the age of system-on-a-chip","authors":"R. Molyneaux","doi":"10.1109/TEST.2003.1271143","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271143","url":null,"abstract":"The current scale of integration is the greatest driving force for needing better and faster, debug capabilities. We are truly building systems on a chip, board level interfaces which could previously be monitored and debugged with logic analyzers are now buried on silicon. We need to consider burying the logic analyzers along with the interfaces. The debug task is sometimes made more difficult in today’s environment with the increased reuse of internal IP, the use of externally supplied IP and remote foundries. Internal reuse of IP may not at first seem like a complicating factor but consider the likely fact that few if any of the original designers of that block are still with the company and you are intending to use it in a design that they had not even thought of. With increased IP reuse our marketing folks, in their infinite wisdom, are tempted to offer more parts in the market, many just a small customization of the base model. “Hey just cut the cache in half, slap on a 10/100 IP block from TI, cut the cost by 30% and we’ve opened up a whole new market!” Right! We are not plug and play in the microprocessor component domain yet. We are executing these design customizations but at this time the extended debug phase may more than compensate for the design time saved due to IP purchase or reuse.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117059194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271160
A. Benso
Today, in the world, there are more embedded systems then people. The use of digital systems pervades all areas of our lives, and this trend of producing digitally-aware environments will keep growing. In the future it will be normal to live surrounded by large numbers of heterogeneous devices, from domestic systems to complex applications like automotive, transportations, and medical control systems, which will communicate together through distributed and wireless interfaces. These complex heterogeneous digital systems will provide higher productivity and greater flexibility, but it is also accepted that they will not be fault-free. Moreover, the percentage of faults detected by any Endof-Production test will not be enough to guarantee the level of availability and reliability required by the market. In this context, the ability of a complex digital system to detect and possibly correct a fault (self-healing) plays a critical role. The state-of-the-art of the research in digital systems’ self-healing has only recently started to address this problem from a system-level point of view.
{"title":"Self-testing and self-healing via mobile agents","authors":"A. Benso","doi":"10.1109/TEST.2003.1271160","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271160","url":null,"abstract":"Today, in the world, there are more embedded systems then people. The use of digital systems pervades all areas of our lives, and this trend of producing digitally-aware environments will keep growing. In the future it will be normal to live surrounded by large numbers of heterogeneous devices, from domestic systems to complex applications like automotive, transportations, and medical control systems, which will communicate together through distributed and wireless interfaces. These complex heterogeneous digital systems will provide higher productivity and greater flexibility, but it is also accepted that they will not be fault-free. Moreover, the percentage of faults detected by any Endof-Production test will not be enough to guarantee the level of availability and reliability required by the market. In this context, the ability of a complex digital system to detect and possibly correct a fault (self-healing) plays a critical role. The state-of-the-art of the research in digital systems’ self-healing has only recently started to address this problem from a system-level point of view.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"45 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271156
S. Eichenberger
It used to be that DfM meant simple recipes such as spreading wires equally across all available space or to double vias where possible. Today, wire spreading is competing with strict density rules and tiling requirements, via doubling is competing with the added stress caused by the additional holes. Still, these simple cases of DfM need nothing more than detailed understanding of process mechanics and a seamless implementation in automated layout tools – the latter could arguably use some more attention!
{"title":"Design for manufacturability - or the meaning of 'subtle'","authors":"S. Eichenberger","doi":"10.1109/TEST.2003.1271156","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271156","url":null,"abstract":"It used to be that DfM meant simple recipes such as spreading wires equally across all available space or to double vias where possible. Today, wire spreading is competing with strict density rules and tiling requirements, via doubling is competing with the added stress caused by the additional holes. Still, these simple cases of DfM need nothing more than detailed understanding of process mechanics and a seamless implementation in automated layout tools – the latter could arguably use some more attention!","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"65 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271105
H. Stratigopoulos, Y. Makris
We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in general, much smaller than a duplicate of the circuit under test. The error detection circuit monitors the input and some j u diciously selected observable internal nodes of the examined circuit to produce an estimate of its output. In error-free operation, this estimate converges to the actual output value in a time interval that can be controlled to be suficiently small. From then onwards, it follows exactly the output. The estimate is constructed such that it does not converge in the presence of errors and, thus, concurrent error detection is pegomzed by comparing the two signals through an analog checkel: The derived theory is validated through representative simulations on two filter examples.
{"title":"Concurrent error detection in linear analog circuits using state estimation","authors":"H. Stratigopoulos, Y. Makris","doi":"10.1109/TEST.2003.1271105","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271105","url":null,"abstract":"We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in general, much smaller than a duplicate of the circuit under test. The error detection circuit monitors the input and some j u diciously selected observable internal nodes of the examined circuit to produce an estimate of its output. In error-free operation, this estimate converges to the actual output value in a time interval that can be controlled to be suficiently small. From then onwards, it follows exactly the output. The estimate is constructed such that it does not converge in the presence of errors and, thus, concurrent error detection is pegomzed by comparing the two signals through an analog checkel: The derived theory is validated through representative simulations on two filter examples.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128370162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270838
A. Syed
NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +I81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.
{"title":"RIC/DICMOS - multichannel CMOS formatter","authors":"A. Syed","doi":"10.1109/TEST.2003.1270838","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270838","url":null,"abstract":"NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +I81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127167226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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