Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270832
R. Kundu, R. D. Blanton
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.
{"title":"Path delay test generation for domino logic circuits in the presence of crosstalk","authors":"R. Kundu, R. D. Blanton","doi":"10.1109/TEST.2003.1270832","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270832","url":null,"abstract":"A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"66 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270880
T. P. Warwick
This paper discusses the issues associated causing jitter in the measurement path can be well with removing the effects of the measurement path characterized and simulated, simple methods of in very high speed measurements. Of critical compensating for measurement path error cannot be concern is deterministic jitter caused by the applied. This paper explores this issue and suggests interaction between the measurement path and the two complementary solutions for addressing such device under test. While individual components jitter.
{"title":"Mitigating the effects of the dut interface board and test system parasitics in gigabit-plus measurements","authors":"T. P. Warwick","doi":"10.1109/TEST.2003.1270880","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270880","url":null,"abstract":"This paper discusses the issues associated causing jitter in the measurement path can be well with removing the effects of the measurement path characterized and simulated, simple methods of in very high speed measurements. Of critical compensating for measurement path error cannot be concern is deterministic jitter caused by the applied. This paper explores this issue and suggests interaction between the measurement path and the two complementary solutions for addressing such device under test. While individual components jitter.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128294070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270837
John S. Davis, D. Keezer, O. Liboiron-Ladouceur, K. Bergman
Abstract A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of programmable I/O for testing circuits and systems. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. This technique has been expanded upon to produce greater functionality at higher frequencies. Based upon limitations of current ATE and BIST, the need for the digital test core is described. The test core concept is reviewed within an opto-electronic pattern generator and sampler with an eventual goal of terabit-per-second aggregate data rate. The performance of the device is discussed, and a second application of the digital test core is introduced as a nano-scale wafer-level embedded tester.
{"title":"Application and demonstration of a digital test core: optoelectronic test bed and wafer-level prober","authors":"John S. Davis, D. Keezer, O. Liboiron-Ladouceur, K. Bergman","doi":"10.1109/TEST.2003.1270837","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270837","url":null,"abstract":"Abstract A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of programmable I/O for testing circuits and systems. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. This technique has been expanded upon to produce greater functionality at higher frequencies. Based upon limitations of current ATE and BIST, the need for the digital test core is described. The test core concept is reviewed within an opto-electronic pattern generator and sampler with an eventual goal of terabit-per-second aggregate data rate. The performance of the device is discussed, and a second application of the digital test core is introduced as a nano-scale wafer-level embedded tester.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126773042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270828
Y. Nishizaki, O. Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura
This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.
{"title":"Testing DSM asic with static, /spl delta/IDDQ, and dynamic test suite: implementation and results","authors":"Y. Nishizaki, O. Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura","doi":"10.1109/TEST.2003.1270828","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270828","url":null,"abstract":"This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, DeltaIddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of DeltaIddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, DeltaIddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"38 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271070
J. Walraven
Abstract MEMS processes and components are rapidly changing in device design, processing, and, most importantly, application. This paper will discuss the future challenges faced by the MEMS failure analysis as the field of MEMS (fabrication, component design, and applications) grows. Specific areas of concern for the failure analyst will also be discussed. 1. Introduction MEMS research is a relatively young field compared to ICs. MEMS design, fabrication, packaging, and reliability testing are still in their infancy and require constant revision and improvements now and over the next several years. MEMS failure analyisis (in this context) is a younger field than MEMS fabrication and design. Although MEMS have been around for a number of years, with failure analysis support for production, packaging, testing, and field operation, the tools and techniques required to properly diagnose the root cause of failure need to be upgraded and designed specifically for MEMS failure mechanisms. MEMS failure mechanisms can be as unique as the devices themselves. In ICs, considerable efforts are taken in handling and testing to properly characterize and assess device performance and compare the performance to device specifications. One major difference between ICs and MEMS testing is the environmental conditions. In many instances, ICs are tested in various environments ranging from various temperature and humidity conditions to vacuum and inert gas. In MEMS technology, similar handling and testing procedures are implemented, but the device is required to work with a given environment [1]. Varying the test environment can dramatically change device sensitivity and functionality. The added complexity of mechanical motion requires added care in handling and testing. Fortunately, MEMS has the advantage of leveraging IC FA tools and techniques for MEMS analysis. However, as the number of devices and applications grow, the MEMS failure analyst must become more diverse and multi-disciplinary in their knowledge base to properly diagnose the root cause of failure. This has become clearly evident in the failure analysis of thermally versus electrostatically driven actuators, microbiological and microfluidic devices, optical and RF components, and the wide array of sensors available for use.
{"title":"Future challenges for mems failure analysis","authors":"J. Walraven","doi":"10.1109/TEST.2003.1271070","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271070","url":null,"abstract":"Abstract MEMS processes and components are rapidly changing in device design, processing, and, most importantly, application. This paper will discuss the future challenges faced by the MEMS failure analysis as the field of MEMS (fabrication, component design, and applications) grows. Specific areas of concern for the failure analyst will also be discussed. 1. Introduction MEMS research is a relatively young field compared to ICs. MEMS design, fabrication, packaging, and reliability testing are still in their infancy and require constant revision and improvements now and over the next several years. MEMS failure analyisis (in this context) is a younger field than MEMS fabrication and design. Although MEMS have been around for a number of years, with failure analysis support for production, packaging, testing, and field operation, the tools and techniques required to properly diagnose the root cause of failure need to be upgraded and designed specifically for MEMS failure mechanisms. MEMS failure mechanisms can be as unique as the devices themselves. In ICs, considerable efforts are taken in handling and testing to properly characterize and assess device performance and compare the performance to device specifications. One major difference between ICs and MEMS testing is the environmental conditions. In many instances, ICs are tested in various environments ranging from various temperature and humidity conditions to vacuum and inert gas. In MEMS technology, similar handling and testing procedures are implemented, but the device is required to work with a given environment [1]. Varying the test environment can dramatically change device sensitivity and functionality. The added complexity of mechanical motion requires added care in handling and testing. Fortunately, MEMS has the advantage of leveraging IC FA tools and techniques for MEMS analysis. However, as the number of devices and applications grow, the MEMS failure analyst must become more diverse and multi-disciplinary in their knowledge base to properly diagnose the root cause of failure. This has become clearly evident in the failure analysis of thermally versus electrostatically driven actuators, microbiological and microfluidic devices, optical and RF components, and the wide array of sensors available for use.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126931175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271122
M. Nicolaidis
IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, they become increasingly sensitive to noise which result on unacceptable rates of soft-errors. Furthermore, defect behavior becomes increasingly complex, resulting on increasing numbers of timing and other spurious faults that can escape detection during fabrication testing. This makes increasingly difficult to achieve acceptable reliability levels for future ICs and maintain acceptable cost and quality for IC testing. One important reliability threat is related to single event transients (SET) and single-event upsets (SEU). An SEU is the consequence of a transient current pulse (single event transient), created when a particle strikes a sensitive node of an integrated circuit. When an SET occurring on a memory cell node flips the state of the cell it is transformed to an SEU. Similarly, when an SET occurring on a node of a logic network is propagated through the gates of the network and is captured by a latch as a logic error, it is transformed to an SEU. Atmospheric neutrons affect the operation of modern ICs even at ground level. A few years ago, the energy of the secondary particles produced by the nuclear reaction of neutrons with the matter of an IC was insufficient to affect its operation. However, as we approached 0.1um and use very low supply voltages, the rates of errors induced by cosmic neutrons became unacceptable. Furthermore, alpha particles produced by the disintegration of unstable isotopes of an IC material and its packaging, are another cause of increasing soft error rates. In addition in today technologies, soft errors concern not only memories (which was the case so far) but also logic. One basic reason for the increased sensitivity of logic parts is the reduction of the device size and the Vdd level. Since both the Vdd level and the circuit nodes capacitance Cnode are reduced, the charge stored on a node (Q = Vdd * Cnode) is reduced drastically. Consequently, a significantly lower charge deposed by a particle strike suffices to flip the logic value of a node creating a transient pulse (single event transient or SET), or to flip the state of a storage cell (single event upset). In the past, the probability of occurrence of a soft error in logic parts was drastically lower than in memories, due to the following reasons: (i) the propagation through logic gates can filter the induced transient pulse, and (ii) a transient pulse propagated through a logic network will result in a logic error only if it reaches the input of a latch simultaneously with the latching edge of the clock. For these reasons, traditionally, only memories have been protected against SEUs, even in a radiation hostile environment like space. Unfortunately, deeper submicron scaling increases drastically the sensitivity of logic networks too. In fact, a transient pulse wider than the logic transition time of a gate
{"title":"Reliability threats in VDSM - shortcomings in conventional test and fault tolerance alternatives","authors":"M. Nicolaidis","doi":"10.1109/TEST.2003.1271122","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271122","url":null,"abstract":"IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, they become increasingly sensitive to noise which result on unacceptable rates of soft-errors. Furthermore, defect behavior becomes increasingly complex, resulting on increasing numbers of timing and other spurious faults that can escape detection during fabrication testing. This makes increasingly difficult to achieve acceptable reliability levels for future ICs and maintain acceptable cost and quality for IC testing. One important reliability threat is related to single event transients (SET) and single-event upsets (SEU). An SEU is the consequence of a transient current pulse (single event transient), created when a particle strikes a sensitive node of an integrated circuit. When an SET occurring on a memory cell node flips the state of the cell it is transformed to an SEU. Similarly, when an SET occurring on a node of a logic network is propagated through the gates of the network and is captured by a latch as a logic error, it is transformed to an SEU. Atmospheric neutrons affect the operation of modern ICs even at ground level. A few years ago, the energy of the secondary particles produced by the nuclear reaction of neutrons with the matter of an IC was insufficient to affect its operation. However, as we approached 0.1um and use very low supply voltages, the rates of errors induced by cosmic neutrons became unacceptable. Furthermore, alpha particles produced by the disintegration of unstable isotopes of an IC material and its packaging, are another cause of increasing soft error rates. In addition in today technologies, soft errors concern not only memories (which was the case so far) but also logic. One basic reason for the increased sensitivity of logic parts is the reduction of the device size and the Vdd level. Since both the Vdd level and the circuit nodes capacitance Cnode are reduced, the charge stored on a node (Q = Vdd * Cnode) is reduced drastically. Consequently, a significantly lower charge deposed by a particle strike suffices to flip the logic value of a node creating a transient pulse (single event transient or SET), or to flip the state of a storage cell (single event upset). In the past, the probability of occurrence of a soft error in logic parts was drastically lower than in memories, due to the following reasons: (i) the propagation through logic gates can filter the induced transient pulse, and (ii) a transient pulse propagated through a logic network will result in a logic error only if it reaches the input of a latch simultaneously with the latching edge of the clock. For these reasons, traditionally, only memories have been protected against SEUs, even in a radiation hostile environment like space. Unfortunately, deeper submicron scaling increases drastically the sensitivity of logic networks too. In fact, a transient pulse wider than the logic transition time of a gate ","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"11 3‐4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270862
T. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, S. Lai
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.
{"title":"Bist for deep submicron asic memories with high performance application","authors":"T. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, S. Lai","doi":"10.1109/TEST.2003.1270862","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270862","url":null,"abstract":"Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123869238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270831
Xiaoliang Bai, S. Dey, Angela Krstic
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk noise generated by coupling capacitances between wires. Test vectors that activate and propagate crosstalk noise effects are becoming an essential part of design verification and manufacturing test. However, deriving such vectors is a complex task. In this paper, we propose HyAC, a fast yet accurate hybrid ATPG method targeting multiple-aggressor induced crosstalk errors. Given a victim and a set of aggressors, the proposed ATPG method searches for test vectors to activate and propagate a crosstalk error for the victim. Due to logic constraints, it may not be possible to trigger all aggressors simultaneously. Therefore, firstly we use an implication graph (IG) that consists of logic variables and structural information to check for logic conflicts. If the current set of aggressors is not feasible, our algorithm automatically searches for the next-best subset of aggressors (resulting in the largest noise). After a set of feasible aggressors is identified, we use a modified PODEM [21] algorithm to search for test vectors. This hybrid structural SAT-based ATPG method inherits advantages from both Boolean- satisfiabilitity based methods and structural-based methods to achieve flexibility and efficiency. We demonstrate the accuracy, high quality, and run time efficiency of HyAC through experiments conducted on several benchmark circuits as well as a circuit from a commercial processor.
{"title":"Hyac: a hybrid structural sat based atpg for crosstalk","authors":"Xiaoliang Bai, S. Dey, Angela Krstic","doi":"10.1109/TEST.2003.1270831","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270831","url":null,"abstract":"As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk noise generated by coupling capacitances between wires. Test vectors that activate and propagate crosstalk noise effects are becoming an essential part of design verification and manufacturing test. However, deriving such vectors is a complex task. In this paper, we propose HyAC, a fast yet accurate hybrid ATPG method targeting multiple-aggressor induced crosstalk errors. Given a victim and a set of aggressors, the proposed ATPG method searches for test vectors to activate and propagate a crosstalk error for the victim. Due to logic constraints, it may not be possible to trigger all aggressors simultaneously. Therefore, firstly we use an implication graph (IG) that consists of logic variables and structural information to check for logic conflicts. If the current set of aggressors is not feasible, our algorithm automatically searches for the next-best subset of aggressors (resulting in the largest noise). After a set of feasible aggressors is identified, we use a modified PODEM [21] algorithm to search for test vectors. This hybrid structural SAT-based ATPG method inherits advantages from both Boolean- satisfiabilitity based methods and structural-based methods to achieve flexibility and efficiency. We demonstrate the accuracy, high quality, and run time efficiency of HyAC through experiments conducted on several benchmark circuits as well as a circuit from a commercial processor.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124207281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270905
P. Dahlgren, P. Dickinson, I. Parulkar
This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Divergence Analysis (LDA) is proposed for creating stable failure signatures and reducing system noise. The methodology and processing flow have been integrated into the normal debug flow for the UltraSPARCTM family processors and have been successfully applied in numerous debugs in the bring-up of new products.
{"title":"Latch divergency in microprocessor failure analysis","authors":"P. Dahlgren, P. Dickinson, I. Parulkar","doi":"10.1109/TEST.2003.1270905","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270905","url":null,"abstract":"This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Divergence Analysis (LDA) is proposed for creating stable failure signatures and reducing system noise. The methodology and processing flow have been integrated into the normal debug flow for the UltraSPARCTM family processors and have been successfully applied in numerous debugs in the bring-up of new products.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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