Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270839
Maurizio Gavardoni
. . Abstract An open architecture tester allows a third party to develop its own instrument. Such a tester must be open in the sense that i f needs to be able to integrate this instrument with minimal or no impact on the overall performance and cost. It is therefore fundamental that the data flow and synchronization among all the instruments in an open architecture tester be efficient. One of these two key topics, the data flow, is discussed in this paper. Some possible solutions that optimize the data flow are presented and one among them is given in full detail. Synchronization is a very wide topic whose discussion could be the subject for a separate paper.
{"title":"Data flow within an open architecture tester","authors":"Maurizio Gavardoni","doi":"10.1109/TEST.2003.1270839","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270839","url":null,"abstract":". . Abstract An open architecture tester allows a third party to develop its own instrument. Such a tester must be open in the sense that i f needs to be able to integrate this instrument with minimal or no impact on the overall performance and cost. It is therefore fundamental that the data flow and synchronization among all the instruments in an open architecture tester be efficient. One of these two key topics, the data flow, is discussed in this paper. Some possible solutions that optimize the data flow are presented and one among them is given in full detail. Synchronization is a very wide topic whose discussion could be the subject for a separate paper.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115932026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271208
K. Parker
A new coverage definition and metric, called the 'PCOLA/SOQ" model, introduced in K. Hird et al. (2002), has great utility in allowing the test coverage of defects on boards to be measured and compared rationally. This paper discusses the general topic of measuring test coverage of boundary-scan tests within this framework. A conclusion is that boundary-scan tests offer a large amount of test coverage when boundary-scan is implemented on a board, even if that implementation is partial. However, coverage is not perfect for certain defects in the PCOLA/SOQ model, as shown by example.
K. Hird等人(2002)引入了一种新的覆盖定义和度量，称为“PCOLA/SOQ”模型，它在允许对电路板上缺陷的测试覆盖进行合理的测量和比较方面具有很大的效用。本文在此框架下讨论了测量边界扫描测试覆盖率的一般问题。结论是，当在电路板上实现边界扫描时，边界扫描测试提供了大量的测试覆盖率，即使该实现是部分的。然而，如示例所示，对于PCOLA/SOQ模型中的某些缺陷，覆盖率并不完美。
{"title":"Defect coverage of boundary-scan tests: what does it mean when a boundary-scan test passes?","authors":"K. Parker","doi":"10.1109/TEST.2003.1271208","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271208","url":null,"abstract":"A new coverage definition and metric, called the 'PCOLA/SOQ\" model, introduced in K. Hird et al. (2002), has great utility in allowing the test coverage of defects on boards to be measured and compared rationally. This paper discusses the general topic of measuring test coverage of boundary-scan tests within this framework. A conclusion is that boundary-scan tests offer a large amount of test coverage when boundary-scan is implemented on a board, even if that implementation is partial. However, coverage is not perfect for certain defects in the PCOLA/SOQ model, as shown by example.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270882
Y. Okuda, N. Furukawa
Empirical analyses of the IDDQ signatures of 0.18 p m devices indicate that IDDQ currents exhibit hysteresis. A newly proposed test method, SPIRIT (Single Pattern Iteration lDDQ Test), demonstrates that the test pattern and the device clock speed before measurements must be maintained to assure the integrity of IDDe measurements, which is the fundamental assumption of IDDQ applications: testing, diagnosis, monitoring, and static power estimation. Newly proposed IDDQ signature and hysteresis models show that hysteresis phenomena are caused by the global transient threshold voltage shifts induced by the direct tunnel charges to the pre-existing border traps under nominal operating conditions.
对0.18 p m器件的IDDQ特征进行的实证分析表明，IDDQ电流存在滞后性。一种新提出的测试方法SPIRIT(单模式迭代lDDQ测试)表明，必须保持测量前的测试模式和器件时钟速度，以确保IDDe测量的完整性，这是IDDQ应用的基本假设:测试、诊断、监测和静态功率估计。新提出的IDDQ特征和迟滞模型表明，迟滞现象是由于在额定工作条件下，直接隧道电荷对预先存在的边界陷阱引起的全局瞬态阈值电压偏移引起的。
{"title":"Hysteresis of intrinsic I/sub DDQ/ currents","authors":"Y. Okuda, N. Furukawa","doi":"10.1109/TEST.2003.1270882","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270882","url":null,"abstract":"Empirical analyses of the IDDQ signatures of 0.18 p m devices indicate that IDDQ currents exhibit hysteresis. A newly proposed test method, SPIRIT (Single Pattern Iteration lDDQ Test), demonstrates that the test pattern and the device clock speed before measurements must be maintained to assure the integrity of IDDe measurements, which is the fundamental assumption of IDDQ applications: testing, diagnosis, monitoring, and static power estimation. Newly proposed IDDQ signature and hysteresis models show that hysteresis phenomena are caused by the global transient threshold voltage shifts induced by the direct tunnel charges to the pre-existing border traps under nominal operating conditions.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117243477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270854
Yu Huang, Wu-Tung Cheng, S. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed a s well. Unlike the previous scan chain diagnosis methods that targeted p ermanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location o f candidate faulty scan cells is obtained. Second a n ew method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of t he bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains.
{"title":"Statistical diagnosis for intermittent scan chain hold-time fault","authors":"Yu Huang, Wu-Tung Cheng, S. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung","doi":"10.1109/TEST.2003.1270854","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270854","url":null,"abstract":"Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed a s well. Unlike the previous scan chain diagnosis methods that targeted p ermanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location o f candidate faulty scan cells is obtained. Second a n ew method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of t he bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115281273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271113
E. Chmelaf
Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented.
{"title":"Fpga interconnect delay fault testing","authors":"E. Chmelaf","doi":"10.1109/TEST.2003.1271113","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271113","url":null,"abstract":"Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116060364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271098
Jayashree Saxena, K. Butler, Vinay B. Jayaram, Subhendu Kundu, N. Arvind, Pravin Sreeprakash, Manfred Hachinger
At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or "switching density" during struc- tured at-speed tests. In Section 3.4 we describe the notion of "quiet" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.
{"title":"A case study of ir-drop in structured at-speed testing","authors":"Jayashree Saxena, K. Butler, Vinay B. Jayaram, Subhendu Kundu, N. Arvind, Pravin Sreeprakash, Manfred Hachinger","doi":"10.1109/TEST.2003.1271098","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271098","url":null,"abstract":"At-speed test has become a requirement in IC tech- nologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special chal- lenges to the successful application of structural at- speed tests. In this paper we characterize these prob- lems on commercial ASICs in order to understand how to implement more effective solutions. consumption. Depending on such parameters as gate count, DFT strategies, package type, and other fac- tors, the impact of this problem can range from non- existent to severe. In this paper, we discuss the prac- tical issues associated with power consumption during at-speed tests. We begin by delineating in more detail the nature of power-related phenomena encountered in structured speed tests. We talk about various de- sign features that can be applied to somewhat miti- gate test mode power dissipation. In Section 2, we give a more precise definition of the IR-drop problem which is the focus of this pa- per. We compare IR-drop in slow speed and at-speed structural tests, and also compare it with functional IR-drop. We narrow the focus further to the topic of toggle activity or \"switching density\" during struc- tured at-speed tests. In Section 3.4 we describe the notion of \"quiet\" patterns and how they are gener- ated. We follow up with a report of the results we have obtained in experimentation on industrial ASIC designs. Finally we give our suggestions for future work in this area and conclude the paper.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116193967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270913
Daniel Fan, Steve Roehling, Rusty Carruth
This paper describes the implementation of a test pattern language using STIL [1], the IEEE Standard Test Interface Language (1450-1999), in a next generation, open architecture Automated Test Equipment (ATE) platform. The advantages of this approach in extensibility and easy interface with Electronic Design Automation (EDA) tools for the ATE user are presented. Some challenges of using STIL as a general purpose ATE test pattern language are also presented. The overall EDA and ATE strategy and pattern system architecture based upon STIL are discussed.
{"title":"Case study - using stil as test pattern language","authors":"Daniel Fan, Steve Roehling, Rusty Carruth","doi":"10.1109/TEST.2003.1270913","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270913","url":null,"abstract":"This paper describes the implementation of a test pattern language using STIL [1], the IEEE Standard Test Interface Language (1450-1999), in a next generation, open architecture Automated Test Equipment (ATE) platform. The advantages of this approach in extensibility and easy interface with Electronic Design Automation (EDA) tools for the ATE user are presented. Some challenges of using STIL as a general purpose ATE test pattern language are also presented. The overall EDA and ATE strategy and pattern system architecture based upon STIL are discussed.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127506603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271083
O. Caty, I. Bayraktaroglu, Amitava Majumdar, Richard Lee, J. Bell, L. Curhan
This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce boardhystem manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable MARCH algorithms and data backgrounds) to enable proper testing of all diflerentjavors of memories and caches that one encounters in systems today. Another important aspect of the methodology is its reuse of on-chip memorykache controllers. This allows the adaptation of the methodology to a variety of memory access protocols (including DDR), without having to re-implement the access protocol inside the BIST engine. These considerations make the External BIST methodology presented in the papei; very general and adaptable to a wide range of applications and their corresponding memory sub-systems.
{"title":"Instruction based bist for board/system level test of external memories and internconnects","authors":"O. Caty, I. Bayraktaroglu, Amitava Majumdar, Richard Lee, J. Bell, L. Curhan","doi":"10.1109/TEST.2003.1271083","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271083","url":null,"abstract":"This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce boardhystem manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable MARCH algorithms and data backgrounds) to enable proper testing of all diflerentjavors of memories and caches that one encounters in systems today. Another important aspect of the methodology is its reuse of on-chip memorykache controllers. This allows the adaptation of the methodology to a variety of memory access protocols (including DDR), without having to re-implement the access protocol inside the BIST engine. These considerations make the External BIST methodology presented in the papei; very general and adaptable to a wide range of applications and their corresponding memory sub-systems.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271150
Ulrich Schoettmer, B. Laquai
The multi-drop buses transform into an on-board packet switched network connecting high-performance chips with differential high-speed point-to-point links. Serial ATA is leading the pack, PCI-Express is emerging, just to name a few, they will soon be common-place to the PC industry. Chipsets in the computation and consumer space are under severe cost pressure, which creates a severe challenge to the traditional test strategies.
{"title":"Managing the multi-gbit/s test challenges","authors":"Ulrich Schoettmer, B. Laquai","doi":"10.1109/TEST.2003.1271150","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271150","url":null,"abstract":"The multi-drop buses transform into an on-board packet switched network connecting high-performance chips with differential high-speed point-to-point links. Serial ATA is leading the pack, PCI-Express is emerging, just to name a few, they will soon be common-place to the PC industry. Chipsets in the computation and consumer space are under severe cost pressure, which creates a severe challenge to the traditional test strategies.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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