Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270834
M. Velev
The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.
{"title":"Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs","authors":"M. Velev","doi":"10.1109/TEST.2003.1270834","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270834","url":null,"abstract":"The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132567397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270889
Qiang Xu, N. Nicolici
Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of wrapper boundary register cells. Since the very purpose of core wrappers is to provide controllability and observability for the cores-under-test, it is shown how the number of wrapper boundary register cells can be reduced without affecting the test quality. While a testing time overhead, caused by lower test concurrency, is incurred, there are clear bene$ts in reducing the necessary DFT area and especially in decreasing the propagation delays, which can improve the SOC’s functional timing performance.
{"title":"On reducing wrapper boundary register cells in modular soc testing","authors":"Qiang Xu, N. Nicolici","doi":"10.1109/TEST.2003.1270889","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270889","url":null,"abstract":"Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of wrapper boundary register cells. Since the very purpose of core wrappers is to provide controllability and observability for the cores-under-test, it is shown how the number of wrapper boundary register cells can be reduced without affecting the test quality. While a testing time overhead, caused by lower test concurrency, is incurred, there are clear bene$ts in reducing the necessary DFT area and especially in decreasing the propagation delays, which can improve the SOC’s functional timing performance.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127518651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270907
T. McLaurin, F. Frederick, R. Slobodnik
The DFT and Test challenges faced, and the solutions applied, to the ARMl026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that will ultimately end up in many different environments. This core was instantiated into a test chip. The new DFT features were utilized successfully in the SOC.
{"title":"The testability features of the ARM1026EJ microprocessor core","authors":"T. McLaurin, F. Frederick, R. Slobodnik","doi":"10.1109/TEST.2003.1270907","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270907","url":null,"abstract":"The DFT and Test challenges faced, and the solutions applied, to the ARMl026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that will ultimately end up in many different environments. This core was instantiated into a test chip. The new DFT features were utilized successfully in the SOC.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114114057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270835
A. Hekmatpour, James Coulter
This paper describes a functional verification methodology based on a system developed at the IBM Microelectronics Embedded PowerPC Design Center, in order to improve the coverage and convergence of random test generators in general and model-based random test generators in particular. It outlines specific tasks and methods devised for qualifying the test generators at various stages of the functional verification process to ensure the integrity of generated tests. It describes methods for calibrating the test generation process to improve functional coverage. In addition, it outlines a strategy for improved management and control of the test generation for faster convergence across corner cases, complex scenarios, and deep interdependencies. The described methodology and its associated verification platform are deployed at the IBM Embedded PowerPC Design Center in Research Triangle Park, North Carolina and has been used in the verification of 4XX and 4XXFPU family of PowerPC Processors.
{"title":"Coverage-directed management and optimization of random functional verification","authors":"A. Hekmatpour, James Coulter","doi":"10.1109/TEST.2003.1270835","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270835","url":null,"abstract":"This paper describes a functional verification methodology based on a system developed at the IBM Microelectronics Embedded PowerPC Design Center, in order to improve the coverage and convergence of random test generators in general and model-based random test generators in particular. It outlines specific tasks and methods devised for qualifying the test generators at various stages of the functional verification process to ensure the integrity of generated tests. It describes methods for calibrating the test generation process to improve functional coverage. In addition, it outlines a strategy for improved management and control of the test generation for faster convergence across corner cases, complex scenarios, and deep interdependencies. The described methodology and its associated verification platform are deployed at the IBM Embedded PowerPC Design Center in Research Triangle Park, North Carolina and has been used in the verification of 4XX and 4XXFPU family of PowerPC Processors.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121510802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270886
Wangqi Qiu, D.M.H. Walker
Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288.
{"title":"An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit","authors":"Wangqi Qiu, D.M.H. Walker","doi":"10.1109/TEST.2003.1270886","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270886","url":null,"abstract":"Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270866
T. Yoneda, T. Uchiyama, H. Fujiwara
This paper presents an area overhead and test time cooptimization method for SoCs based on consecutive testability. Consecutive testability of SoCs guarantees that we can handle any test sequence that requires consecutive application of test patterns at speed of system clock such as a test sequence for timing faults. The proposed method creates a test schedule and TAM using existing interconnects as much as possible. Moreover, the method allows tradeoff between area overhead and test time according to user defined ratio. Experimental results show that the proposed method can achieve lower area overhead compared to test bus architecture due to the utilization of existing interconnects as a part of TAM. keywords: system-on-a-chip, design for testability, test access mechanism, test scheduling, consecutive testability
{"title":"Area and time co-optimization for system-on-a-chip based on consecutive testability","authors":"T. Yoneda, T. Uchiyama, H. Fujiwara","doi":"10.1109/TEST.2003.1270866","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270866","url":null,"abstract":"This paper presents an area overhead and test time cooptimization method for SoCs based on consecutive testability. Consecutive testability of SoCs guarantees that we can handle any test sequence that requires consecutive application of test patterns at speed of system clock such as a test sequence for timing faults. The proposed method creates a test schedule and TAM using existing interconnects as much as possible. Moreover, the method allows tradeoff between area overhead and test time according to user defined ratio. Experimental results show that the proposed method can achieve lower area overhead compared to test bus architecture due to the utilization of existing interconnects as a part of TAM. keywords: system-on-a-chip, design for testability, test access mechanism, test scheduling, consecutive testability","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115376742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271219
Tapio Koivukangas
This environment is an undoubtedly very complex one containing devices from different product manufacturers (mobile terminals, base stations, wireless applications.. .). The amount of different kind of wireless applications will he huge. This is a big challenge also for testing e.g. how to locate the fault quickly, reliably and accurately and how to ensure interoperahility (IOP) between the devices already in R&D ohase before the actual Droduct launch.
{"title":"Testing challenges of future wireless world","authors":"Tapio Koivukangas","doi":"10.1109/TEST.2003.1271219","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271219","url":null,"abstract":"This environment is an undoubtedly very complex one containing devices from different product manufacturers (mobile terminals, base stations, wireless applications.. .). The amount of different kind of wireless applications will he huge. This is a big challenge also for testing e.g. how to locate the fault quickly, reliably and accurately and how to ensure interoperahility (IOP) between the devices already in R&D ohase before the actual Droduct launch.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124925842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271109
M. Mishra, S. Goldstein
As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.
{"title":"Defect tolerance at the end of the roadmap","authors":"M. Mishra, S. Goldstein","doi":"10.1109/TEST.2003.1271109","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271109","url":null,"abstract":"As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128794136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271077
B. K. Kumar, P. Lala
Paper 35.3 91 2 from the previous stage. If the actual carry-in is ‘0’ then the sum multiplexed from the first unit is selected, alternatively if the carry-in is. ‘ 1 ’ then the sum from the second unit is selected. A carry select adder of arbitrary size can be deigned by cascading together an appropriate number of such 4-bit adders. This paper concentrates on designing a scheme for implementing self-checking carry-select adders. Several techniques have been proposed in recent years for designing self-checking adders [2][3][4]. Coding techniques such as Berger code, Residue code and arithmetic codes have been proposed for checking the hnctionality of the arithmetic units. a3 b3 a2 b2 al b l QO bO
{"title":"On-line detection of faults in carry-select adders","authors":"B. K. Kumar, P. Lala","doi":"10.1109/TEST.2003.1271077","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271077","url":null,"abstract":"Paper 35.3 91 2 from the previous stage. If the actual carry-in is ‘0’ then the sum multiplexed from the first unit is selected, alternatively if the carry-in is. ‘ 1 ’ then the sum from the second unit is selected. A carry select adder of arbitrary size can be deigned by cascading together an appropriate number of such 4-bit adders. This paper concentrates on designing a scheme for implementing self-checking carry-select adders. Several techniques have been proposed in recent years for designing self-checking adders [2][3][4]. Coding techniques such as Berger code, Residue code and arithmetic codes have been proposed for checking the hnctionality of the arithmetic units. a3 b3 a2 b2 al b l QO bO","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127832173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271103
T. Waayers
Abstract This paper presents improvement of a core-based chip™s test control architecture that uses Std IEEE 1149.1 TAP to access core level register Test Control Blocks (TCB). We show enhancements for the register TCB, to improve its test coverage, to enable IEEE 1149.1 compliant RUNBIST and to optimize chip level TCB access. In addition, Test Control Expansion (TCE) is presented. TCE automatically validates test control architecture in a design netlist, and is capable of calculating chip level test mode initialization sequences. 1. Introduction ‚Divide and conquer™, a well-known strategy that was born in ancient times. Needless to say that it is still alive and an absolute must in today™s system chip design. Modern system chips are built by merging IP cores, which are often delivered from several companies. Each core providing company focuses on their own expertise. This enables the development of innovative, high quality products in reasonable time. Given the amount of resources active in the design domain, multiple cores can be developed in the same time frame. These cores find their way into multiple designs, serving a variety of application areas. The ease of merging IP delivered from more than one source, heavily correlates with the availability of a robust re-use strategy. Such a strategy leads to ‚conquer™ by not only ‚divide™ in the functional domain, but in the test domain as well. For this reason the IEEE P1500 Working Group [13] pursues a standard for testing embedded cores. It tries to define a standard that facilitates the test interoperability of IP cores from different sources. Ideally this results in a ‚plug & play™ environment in which tests delivered with a core can be executed, without modifications, even when this core is deeply embedded in a large system chip. The conceptual architecture for testing embedded cores in system chips, consists of a pattern source and sink, a test access mechanism and a core test wrapper [4]. These elements are often discussed in relation with test data reduction, test time optimization and test scheduling. In this paper we deal with the accompanying test control. We present a test control concept that makes use of hardware structures, similar to the TCB defined by the Virtual Socket Interface Alliance (VSIA). This test control hardware also can be seen as a subset of the IEEE P1500 Wrapper Instruction Register (WIR). Besides improvement and new features in hardware we introduce a unique tool flow that is currently used to generate, and efficiently evaluate, test control for large system chips. The sequel of this paper is organized as follows. Section 2 gives an overview of prior work done in the domain of test control hardware. Section 2.1 introduces the Philips Test Control Architecture. In section 3 features are presented that improve the test coverage of both TCB and the logic it controls. It also describes a mechanism to implement test control for the standard IEEE 1149.1 runbist instructio
{"title":"An improved test control architecture and test control expansion for core-based system chips","authors":"T. Waayers","doi":"10.1109/TEST.2003.1271103","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271103","url":null,"abstract":"Abstract This paper presents improvement of a core-based chip™s test control architecture that uses Std IEEE 1149.1 TAP to access core level register Test Control Blocks (TCB). We show enhancements for the register TCB, to improve its test coverage, to enable IEEE 1149.1 compliant RUNBIST and to optimize chip level TCB access. In addition, Test Control Expansion (TCE) is presented. TCE automatically validates test control architecture in a design netlist, and is capable of calculating chip level test mode initialization sequences. 1. Introduction ‚Divide and conquer™, a well-known strategy that was born in ancient times. Needless to say that it is still alive and an absolute must in today™s system chip design. Modern system chips are built by merging IP cores, which are often delivered from several companies. Each core providing company focuses on their own expertise. This enables the development of innovative, high quality products in reasonable time. Given the amount of resources active in the design domain, multiple cores can be developed in the same time frame. These cores find their way into multiple designs, serving a variety of application areas. The ease of merging IP delivered from more than one source, heavily correlates with the availability of a robust re-use strategy. Such a strategy leads to ‚conquer™ by not only ‚divide™ in the functional domain, but in the test domain as well. For this reason the IEEE P1500 Working Group [13] pursues a standard for testing embedded cores. It tries to define a standard that facilitates the test interoperability of IP cores from different sources. Ideally this results in a ‚plug & play™ environment in which tests delivered with a core can be executed, without modifications, even when this core is deeply embedded in a large system chip. The conceptual architecture for testing embedded cores in system chips, consists of a pattern source and sink, a test access mechanism and a core test wrapper [4]. These elements are often discussed in relation with test data reduction, test time optimization and test scheduling. In this paper we deal with the accompanying test control. We present a test control concept that makes use of hardware structures, similar to the TCB defined by the Virtual Socket Interface Alliance (VSIA). This test control hardware also can be seen as a subset of the IEEE P1500 Wrapper Instruction Register (WIR). Besides improvement and new features in hardware we introduce a unique tool flow that is currently used to generate, and efficiently evaluate, test control for large system chips. The sequel of this paper is organized as follows. Section 2 gives an overview of prior work done in the domain of test control hardware. Section 2.1 introduces the Philips Test Control Architecture. In section 3 features are presented that improve the test coverage of both TCB and the logic it controls. It also describes a mechanism to implement test control for the standard IEEE 1149.1 runbist instructio","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126997401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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