Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484337
S. Cogley
In today's highly competitive business environment, manufacturers must decrease costs and maximize tool usage to maintain a competitive edge. IBM's semiconductor manufacturing facility in Essex Junction, Vermont, is no exception to the rule. In the early 1990s, this facility took a hard look at all of the factors that contributed to the cost of its products. Major sources of spending in a device fabricator like IBM's are those expenses incurred in maintaining machines and equipment-in particular, spare parts for repair and the routine maintenance of equipment. The increased awareness of costs associated with maintaining manufacturing equipment has also brought a renewed focus to spare parts. Although these costs can be enormous, then are also significant opportunities for savings. Unfortunately, discovering these savings can be a difficult and time-consuming task, if people looking for the savings do not have a through understanding of how individual tools function. On the other hand, if the real costs of equipment maintenance are not known, it is difficult to determine where and how to realize savings. This paper describes how manufacturing personnel learned to use IBM's financial reporting systems to find these savings and reduce the use of spare parts.
{"title":"Cost reduction in a manufacturing fabricator: from the bottom up","authors":"S. Cogley","doi":"10.1109/ASMC.1995.484337","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484337","url":null,"abstract":"In today's highly competitive business environment, manufacturers must decrease costs and maximize tool usage to maintain a competitive edge. IBM's semiconductor manufacturing facility in Essex Junction, Vermont, is no exception to the rule. In the early 1990s, this facility took a hard look at all of the factors that contributed to the cost of its products. Major sources of spending in a device fabricator like IBM's are those expenses incurred in maintaining machines and equipment-in particular, spare parts for repair and the routine maintenance of equipment. The increased awareness of costs associated with maintaining manufacturing equipment has also brought a renewed focus to spare parts. Although these costs can be enormous, then are also significant opportunities for savings. Unfortunately, discovering these savings can be a difficult and time-consuming task, if people looking for the savings do not have a through understanding of how individual tools function. On the other hand, if the real costs of equipment maintenance are not known, it is difficult to determine where and how to realize savings. This paper describes how manufacturing personnel learned to use IBM's financial reporting systems to find these savings and reduce the use of spare parts.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484403
K. Wells, D. Parker, K. Pashby
Customer satisfaction in the semiconductor business depends on the ability of manufacturers to provide on-time delivery of quality products. To meet this objective without increasing resources, fabricator productivity must be maximized. At the IBM Microelectronics Division 200-mm semiconductor fabricator in Essex Junction, Vermont, the alternate work schedule (AWS) N1 Team enhanced its productivity by giving responsibility for this key measurement to a team of three nonmanagers. This paper describes how the team increased productivity to a point equal to or better than the measurement stipulated in the fabricator's strategic operating plan. Referred to as the OF-OUT Team, the group focused on moving 14 individual departments comprising the N1 Team to a working arrangement that focused on the team as a whole rather than on the sum of its parts. This concept placed a premium on people working together as a team so that the productivity of each individual could be maximized. By adhering to this concept, the N1 Team realized a 4.7% increase in average daily operational productivity over its first six months without an increase in resources. This improvement occurred by setting one goal for the entire team, challenging the individual operators to find the procedural changes necessary to meet this goal and by bringing people together from different departments to solve problems that ordinarily would be outside their areas of control. The teamwork approach to operational productivity is used today by various departments to examine how they do business and to look for opportunities where this change in strategy can benefit both other departments and the N1 Team as a whole.
{"title":"Developing the methodology to improve productivity within an integrated 200-mm fabricator","authors":"K. Wells, D. Parker, K. Pashby","doi":"10.1109/ASMC.1995.484403","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484403","url":null,"abstract":"Customer satisfaction in the semiconductor business depends on the ability of manufacturers to provide on-time delivery of quality products. To meet this objective without increasing resources, fabricator productivity must be maximized. At the IBM Microelectronics Division 200-mm semiconductor fabricator in Essex Junction, Vermont, the alternate work schedule (AWS) N1 Team enhanced its productivity by giving responsibility for this key measurement to a team of three nonmanagers. This paper describes how the team increased productivity to a point equal to or better than the measurement stipulated in the fabricator's strategic operating plan. Referred to as the OF-OUT Team, the group focused on moving 14 individual departments comprising the N1 Team to a working arrangement that focused on the team as a whole rather than on the sum of its parts. This concept placed a premium on people working together as a team so that the productivity of each individual could be maximized. By adhering to this concept, the N1 Team realized a 4.7% increase in average daily operational productivity over its first six months without an increase in resources. This improvement occurred by setting one goal for the entire team, challenging the individual operators to find the procedural changes necessary to meet this goal and by bringing people together from different departments to solve problems that ordinarily would be outside their areas of control. The teamwork approach to operational productivity is used today by various departments to examine how they do business and to look for opportunities where this change in strategy can benefit both other departments and the N1 Team as a whole.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122553136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484398
E. Rose, R. Odom, R. Murphy, L. Behnke
This paper will describe two Harris Semiconductor success stories and discuss the SDWT (self-directed work team) tools used to be successful. The first story concerns a union factory that, faced with the potential loss of a major customer, tried a new approach to creating dialog between teams from each company. The second story concerns a wafer fabrication line where teams were in place for two years with little signs of improvement. By introducing TOC and TPM, in combination with a structured team environment, the same group of people made significant operational improvements within six months (40% increase in volume, 2x improvement in die yield (quality), 23% reduction in cycle time, and 16% improvement in line yield).
{"title":"SDWT requires tools to be successful","authors":"E. Rose, R. Odom, R. Murphy, L. Behnke","doi":"10.1109/ASMC.1995.484398","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484398","url":null,"abstract":"This paper will describe two Harris Semiconductor success stories and discuss the SDWT (self-directed work team) tools used to be successful. The first story concerns a union factory that, faced with the potential loss of a major customer, tried a new approach to creating dialog between teams from each company. The second story concerns a wafer fabrication line where teams were in place for two years with little signs of improvement. By introducing TOC and TPM, in combination with a structured team environment, the same group of people made significant operational improvements within six months (40% increase in volume, 2x improvement in die yield (quality), 23% reduction in cycle time, and 16% improvement in line yield).","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126503792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484378
B. Metteer
Initial results from SEMATECH and SEMATECH sponsored research indicate great promise for successful commercial thermal shock and thermal NF/sub 3/ in-situ cleaning of furnace process chambers. Use of the technologies on standard diffusion furnaces is highly flexible depending on a production facility's current capacity and process conditions. Research at SEMATECH aimed at optimizing both methodologies will continue into 1996 with all data being completely accessible to SEMATECH member companies.
{"title":"Thermal shock and thermal NF/sub 3/ in-situ furnace cleaning","authors":"B. Metteer","doi":"10.1109/ASMC.1995.484378","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484378","url":null,"abstract":"Initial results from SEMATECH and SEMATECH sponsored research indicate great promise for successful commercial thermal shock and thermal NF/sub 3/ in-situ cleaning of furnace process chambers. Use of the technologies on standard diffusion furnaces is highly flexible depending on a production facility's current capacity and process conditions. Research at SEMATECH aimed at optimizing both methodologies will continue into 1996 with all data being completely accessible to SEMATECH member companies.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125955773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484326
L. Camilletti
This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins for Alpha, indicated the need to strictly control both interand intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will be addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.
{"title":"Implementation of CMP-based design rules and patterning practices","authors":"L. Camilletti","doi":"10.1109/ASMC.1995.484326","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484326","url":null,"abstract":"This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins for Alpha, indicated the need to strictly control both interand intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will be addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129677567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484397
M. Tamaoki, K. Nishiki, A. Shimazaki, Y. Sasaki, S. Yanagi
In this paper we report on the effect of airborne organic contaminants in actual cleanrooms. We have developed methods for the analysis of contaminants adsorbed on wafer surfaces, including thermal desorption-gas chromatography/mass spectrometry (TD-GC/MS) and thermal desorption-atmospheric pressure ionization mass spectrometry (TD-APIMS). From the results of analysis using TD-GC/MS, TD-APIMS, and ion chromatography (IC), we demonstrate that several specific organic compounds in cleanroom air tend to adsorb on silicon wafers. These include dioctyl-phthalate (DOP), other esters, and amines. We have also found that these organic contaminants adsorbed on the wafer surface cause a reduction in the breakdown field strength of an insulating SiO/sub 2/ layer. The origin of DOP and the other esters is the plasticizer added to many polymeric materials. DOP exists in the cleanroom inlet atmosphere, and there are additional outgassings from many polymeric materials in the cleanroom itself. The major source of amine contaminants is chemicals added to the steam which is used for humidity control in the cleanroom. We show that organic contaminants from the wafer carriers and boxes also cause a reduction in the breakdown field strength of a SiO/sub 2/ layer. We also succeed in decreasing organic contaminants by use of adopting charcoal air filtering.
{"title":"The effect of airborne contaminants in the cleanroom for ULSI manufacturing process","authors":"M. Tamaoki, K. Nishiki, A. Shimazaki, Y. Sasaki, S. Yanagi","doi":"10.1109/ASMC.1995.484397","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484397","url":null,"abstract":"In this paper we report on the effect of airborne organic contaminants in actual cleanrooms. We have developed methods for the analysis of contaminants adsorbed on wafer surfaces, including thermal desorption-gas chromatography/mass spectrometry (TD-GC/MS) and thermal desorption-atmospheric pressure ionization mass spectrometry (TD-APIMS). From the results of analysis using TD-GC/MS, TD-APIMS, and ion chromatography (IC), we demonstrate that several specific organic compounds in cleanroom air tend to adsorb on silicon wafers. These include dioctyl-phthalate (DOP), other esters, and amines. We have also found that these organic contaminants adsorbed on the wafer surface cause a reduction in the breakdown field strength of an insulating SiO/sub 2/ layer. The origin of DOP and the other esters is the plasticizer added to many polymeric materials. DOP exists in the cleanroom inlet atmosphere, and there are additional outgassings from many polymeric materials in the cleanroom itself. The major source of amine contaminants is chemicals added to the steam which is used for humidity control in the cleanroom. We show that organic contaminants from the wafer carriers and boxes also cause a reduction in the breakdown field strength of a SiO/sub 2/ layer. We also succeed in decreasing organic contaminants by use of adopting charcoal air filtering.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1959 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484341
A. Diebold
Summary form only given. In-line and off-line metrology measurement and interpretation are a critical, but time consuming part of yield learning. Yield learning occurs during pilot line development and early volume manufacture. Networking analysis systems and whole wafer analysis tools can greatly reduce the cycle time associated with metrology during yield learning. Although in-line metrology tools have whole wafer capability, other tools such as scanning electron microscopes (equipped with energy dispersive spectroscopy: SEM/EDS) for defect review are recent developments. These SEM/EDS defect review tools (DRT) have coordinate locating stages and software capable of reading wafer defect maps from optical defect detection systems. In this paper, we discuss networked analysis systems and whole wafer tools for in/off-line analysis. The issues associated with data interpretation and management become greater with each new technology generation. We also discuss new network capabilities such as presorting electrical defects into similar types before physical characterization using "model yield learning".
{"title":"Networked analysis systems","authors":"A. Diebold","doi":"10.1109/ASMC.1995.484341","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484341","url":null,"abstract":"Summary form only given. In-line and off-line metrology measurement and interpretation are a critical, but time consuming part of yield learning. Yield learning occurs during pilot line development and early volume manufacture. Networking analysis systems and whole wafer analysis tools can greatly reduce the cycle time associated with metrology during yield learning. Although in-line metrology tools have whole wafer capability, other tools such as scanning electron microscopes (equipped with energy dispersive spectroscopy: SEM/EDS) for defect review are recent developments. These SEM/EDS defect review tools (DRT) have coordinate locating stages and software capable of reading wafer defect maps from optical defect detection systems. In this paper, we discuss networked analysis systems and whole wafer tools for in/off-line analysis. The issues associated with data interpretation and management become greater with each new technology generation. We also discuss new network capabilities such as presorting electrical defects into similar types before physical characterization using \"model yield learning\".","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126633673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484381
L. Azzano, D. Gay, A. Pasumamula
When equipment manufacturers conduct reliability enhancement testing, customer process development, and engineering testing, the resource investment needed to support all three efforts can be significant. FSI International operates a unique equipment reliability enhancement program that allows simultaneous process development, reliability and engineering testing. The program groups all three test objectives with the following advantages: 1) Greater operating efficiency gained by multi-tasking a single lab tool; 2) Considerable capital and operating expense savings; and 3) Accelerated learning cycles and quality improvement. The FSI program is based on SEMI E10-92, the Motorola IRONMAN equipment test philosophy, and customer equipment evaluation guidelines. The main principle of the FSI reliability program is continuous 24-hour operation of the tool. Process data is collected at regular intervals and system reliability is tracked continuously. The original program goals were system MTBF/spl ges/1000 hrs. and total system uptime exceeding 99%, while maintaining the tool for engineering and customer application work. The advantages of continuous testing are twofold. First, the equipment design becomes more robust and better able to meet future customer process requirements. Second, a database is created that characterizes the machine on a long-term basis and allows better process predictions to be made. The paper details the testing methodology adopted for this reliability program. It reviews the troubleshooting and corrective action procedure, the status of the program, and summarize the results.
{"title":"A practical approach to equipment reliability enhancement","authors":"L. Azzano, D. Gay, A. Pasumamula","doi":"10.1109/ASMC.1995.484381","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484381","url":null,"abstract":"When equipment manufacturers conduct reliability enhancement testing, customer process development, and engineering testing, the resource investment needed to support all three efforts can be significant. FSI International operates a unique equipment reliability enhancement program that allows simultaneous process development, reliability and engineering testing. The program groups all three test objectives with the following advantages: 1) Greater operating efficiency gained by multi-tasking a single lab tool; 2) Considerable capital and operating expense savings; and 3) Accelerated learning cycles and quality improvement. The FSI program is based on SEMI E10-92, the Motorola IRONMAN equipment test philosophy, and customer equipment evaluation guidelines. The main principle of the FSI reliability program is continuous 24-hour operation of the tool. Process data is collected at regular intervals and system reliability is tracked continuously. The original program goals were system MTBF/spl ges/1000 hrs. and total system uptime exceeding 99%, while maintaining the tool for engineering and customer application work. The advantages of continuous testing are twofold. First, the equipment design becomes more robust and better able to meet future customer process requirements. Second, a database is created that characterizes the machine on a long-term basis and allows better process predictions to be made. The paper details the testing methodology adopted for this reliability program. It reviews the troubleshooting and corrective action procedure, the status of the program, and summarize the results.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125511858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484370
J. Moyne, R. Telfeyan, A. Hunvitz, J. Taylor
The controller design utilizes a Generic Cell Controller (GCC) enabler; thus it is process-independent, and the controller implementation software exhibits a high degree of portability, flexibility, robustness, and reusability. The design also includes a multi-branch R2R control scheme that can incorporate any number of controller algorithms in a complementary fashion. Further, it provides support for data collection, R2R recipe optimization and control, and recipe advice download. The controller implementation is largely hardware and software independent; its operation has been demonstrated on SUN SPARC, Intel 486 and Pentium, and HP PA-RISC platforms. It has a capability to incorporate in dynamic fashion (i.e., during run-time) any number of software modules existing on any of the aforementioned platforms within a distributed environment, resulting in a truly dynamic and distributed solution. The implementation was initially applied to the control of a reactive ion etcher (RIE). More recently it has also been successfully applied to the R2R control of a CMP tool, thus demonstrating process independence. The latter application utilizes a "gradual mode" MIMO linear approximation control algorithm developed at MIT, enhanced to support parameter weighting and advice parameter granularity. Recent results indicate that good control of removal rate with fair control of uniformity has been achieved. Current efforts are focused on development of additional algorithm "branches" to complement the gradual mode control, and on the reduction of process variance through real-time equipment monitoring.
{"title":"A process-independent run-to-run controller and its application to chemical-mechanical planarization","authors":"J. Moyne, R. Telfeyan, A. Hunvitz, J. Taylor","doi":"10.1109/ASMC.1995.484370","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484370","url":null,"abstract":"The controller design utilizes a Generic Cell Controller (GCC) enabler; thus it is process-independent, and the controller implementation software exhibits a high degree of portability, flexibility, robustness, and reusability. The design also includes a multi-branch R2R control scheme that can incorporate any number of controller algorithms in a complementary fashion. Further, it provides support for data collection, R2R recipe optimization and control, and recipe advice download. The controller implementation is largely hardware and software independent; its operation has been demonstrated on SUN SPARC, Intel 486 and Pentium, and HP PA-RISC platforms. It has a capability to incorporate in dynamic fashion (i.e., during run-time) any number of software modules existing on any of the aforementioned platforms within a distributed environment, resulting in a truly dynamic and distributed solution. The implementation was initially applied to the control of a reactive ion etcher (RIE). More recently it has also been successfully applied to the R2R control of a CMP tool, thus demonstrating process independence. The latter application utilizes a \"gradual mode\" MIMO linear approximation control algorithm developed at MIT, enhanced to support parameter weighting and advice parameter granularity. Recent results indicate that good control of removal rate with fair control of uniformity has been achieved. Current efforts are focused on development of additional algorithm \"branches\" to complement the gradual mode control, and on the reduction of process variance through real-time equipment monitoring.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121458547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484383
F. Lee, Ping Wang, R. Goodner
Variations in defect distributions and device yield patterns can provide significant information about the performance of processes used in the fabrication of integrated circuits. This paper describes how signature analysis and visual/electrical correlation were used to identify yield loss mechanisms during the start-up and production ramp of MOS 12, Motorola's newest 8-inch high volume wafer fab. The identification, diagnosis, and resolution of two yield issues are presented as case studies,.
{"title":"Factory start-up and production ramp: yield improvement through signature analysis and visual/electrical correlation","authors":"F. Lee, Ping Wang, R. Goodner","doi":"10.1109/ASMC.1995.484383","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484383","url":null,"abstract":"Variations in defect distributions and device yield patterns can provide significant information about the performance of processes used in the fabrication of integrated circuits. This paper describes how signature analysis and visual/electrical correlation were used to identify yield loss mechanisms during the start-up and production ramp of MOS 12, Motorola's newest 8-inch high volume wafer fab. The identification, diagnosis, and resolution of two yield issues are presented as case studies,.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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