Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484349
J. Achacoso, G. Pisapía
Automated control distribution and execution of equipment recipes rely on the on-line management of data and equipment support for recipe services. The factory's need for recipe management combined with a lack of mature standards have resulted in factory- and tool-specific implementations. The proprietary nature of these solutions has been expensive to develop and maintain for both factories and equipment suppliers. The release of industry standard Recipe Management definitions have sparked a partnership between MEMC (factory) and ADE (supplier) to develop a prototype that validates SEMI's Recipe Management Services standard according to specific requirements of the factory and current equipment capabilities. This partnership allows an equipment supplier to work closely with the factory in identifying and defining functional and connectivity requirements for a CIM-based Recipe Management System. This paper describes MEMC and ADE's cooperative efforts in identifying both factory and equipment requirements for the deployment of industry standard recipe management services.
{"title":"Partnering for the integration of equipment recipe services into an automated factory","authors":"J. Achacoso, G. Pisapía","doi":"10.1109/ASMC.1995.484349","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484349","url":null,"abstract":"Automated control distribution and execution of equipment recipes rely on the on-line management of data and equipment support for recipe services. The factory's need for recipe management combined with a lack of mature standards have resulted in factory- and tool-specific implementations. The proprietary nature of these solutions has been expensive to develop and maintain for both factories and equipment suppliers. The release of industry standard Recipe Management definitions have sparked a partnership between MEMC (factory) and ADE (supplier) to develop a prototype that validates SEMI's Recipe Management Services standard according to specific requirements of the factory and current equipment capabilities. This partnership allows an equipment supplier to work closely with the factory in identifying and defining functional and connectivity requirements for a CIM-based Recipe Management System. This paper describes MEMC and ADE's cooperative efforts in identifying both factory and equipment requirements for the deployment of industry standard recipe management services.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123576703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484330
K. Lowry, C. VanHorn, G. Shawhan
Summary form only given. Momentum for the increased use of plating processes in wafer finishing applications, as an alternative to vapor deposition technology, is occurring in both bump applications and also as a potential replacement to the top layer conductors of the integrated circuit itself. The acceptance of plating technology in the semiconductor industry is predicated upon its ability to satisfy both key technical requirements and, at the same time, effectively address cost of ownership issues. This is especially true for larger area format production where the facility investment required for implementation necessitates significant improvement in all areas of process cost. In general, electroplating offers advantages in both of these areas. This paper discusses new automated, cassette-to-cassette electroplating equipment that has been developed specifically for wafer finishing applications. Included in the presentation will be details of the automation of the system and the expected throughput capabilities for high volume production including 200 mm wafers. Additional cost of ownership issues will be discussed including fixed cost estimates over the life of the system, variable cost estimates relating to the annual operation of the system, system utilization and downtime estimates and process consistency as it relates to potential yield losses. Results of distribution studies on 200 mm wafers carried out in this equipment will also be presented. In particular, electroplated copper, which has its primary application as a conductor replacement for vapor deposited aluminum on the IC itself will be discussed. In addition, lead-tin will also be discussed as it relates to wafer bumping for flip-chip applications. Information will also be included on gold bumping for TAB applications.
{"title":"Advancements in wafer finishing manufacturing technology involving plating","authors":"K. Lowry, C. VanHorn, G. Shawhan","doi":"10.1109/ASMC.1995.484330","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484330","url":null,"abstract":"Summary form only given. Momentum for the increased use of plating processes in wafer finishing applications, as an alternative to vapor deposition technology, is occurring in both bump applications and also as a potential replacement to the top layer conductors of the integrated circuit itself. The acceptance of plating technology in the semiconductor industry is predicated upon its ability to satisfy both key technical requirements and, at the same time, effectively address cost of ownership issues. This is especially true for larger area format production where the facility investment required for implementation necessitates significant improvement in all areas of process cost. In general, electroplating offers advantages in both of these areas. This paper discusses new automated, cassette-to-cassette electroplating equipment that has been developed specifically for wafer finishing applications. Included in the presentation will be details of the automation of the system and the expected throughput capabilities for high volume production including 200 mm wafers. Additional cost of ownership issues will be discussed including fixed cost estimates over the life of the system, variable cost estimates relating to the annual operation of the system, system utilization and downtime estimates and process consistency as it relates to potential yield losses. Results of distribution studies on 200 mm wafers carried out in this equipment will also be presented. In particular, electroplated copper, which has its primary application as a conductor replacement for vapor deposited aluminum on the IC itself will be discussed. In addition, lead-tin will also be discussed as it relates to wafer bumping for flip-chip applications. Information will also be included on gold bumping for TAB applications.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116840436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484386
A. Mirza, G. O'Donoghue, A. W. Drake, S. Graves
The distribution of good and bad chips on a semiconductor wafer typically results in two types of regions, one that contains both good and bad chips distributed in a random fashion, called a "non-zero yield region", and the other that contains almost all bad chips, called a "zero yield region". The yield of a non-zero yield region is modeled by well understood expressions derived from Poisson or negative binomial statistics. To account for yield loss associated with zero yield regions, the yield expression for non-zero yield regions is multiplied by Y/sub 0/, the fraction of the wafer occupied by non-zero yield regions. The presence, extent, and nature of zero yield regions on a given wafer provide information about yield loss mechanisms responsible for causing them. Two statistical methods are developed to detect the presence of zero yield regions and calculate Y/sub 0/ for a given wafer. These methods are based on a set-theoretic image analysis tool, called the Aura Framework, and on hypothesis testing on nearest neighbors of bad chips. Results show that the modeling of the distribution of good and bad chips on wafers in terms of zero and non-zero yield regions is highly accurate. The detection of zero yield regions provides improved insight into the yield loss mechanisms. Also, the ability to calculate Y/sub 0/ enables better evaluation of the yield models used to predict the yield of non-zero yield regions.
{"title":"Spatial yield modeling for semiconductor wafers","authors":"A. Mirza, G. O'Donoghue, A. W. Drake, S. Graves","doi":"10.1109/ASMC.1995.484386","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484386","url":null,"abstract":"The distribution of good and bad chips on a semiconductor wafer typically results in two types of regions, one that contains both good and bad chips distributed in a random fashion, called a \"non-zero yield region\", and the other that contains almost all bad chips, called a \"zero yield region\". The yield of a non-zero yield region is modeled by well understood expressions derived from Poisson or negative binomial statistics. To account for yield loss associated with zero yield regions, the yield expression for non-zero yield regions is multiplied by Y/sub 0/, the fraction of the wafer occupied by non-zero yield regions. The presence, extent, and nature of zero yield regions on a given wafer provide information about yield loss mechanisms responsible for causing them. Two statistical methods are developed to detect the presence of zero yield regions and calculate Y/sub 0/ for a given wafer. These methods are based on a set-theoretic image analysis tool, called the Aura Framework, and on hypothesis testing on nearest neighbors of bad chips. Results show that the modeling of the distribution of good and bad chips on wafers in terms of zero and non-zero yield regions is highly accurate. The detection of zero yield regions provides improved insight into the yield loss mechanisms. Also, the ability to calculate Y/sub 0/ enables better evaluation of the yield models used to predict the yield of non-zero yield regions.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484409
B. Klumpp, J. Schliesser, O. Herzog, P. Staudt-Fischbach
SMIF technology for microelectronic production lines is being increasingly used worldwide. A crucial factor for an economical SMIF solution is the planning phase, where experience has shown that the general approach to the project must aim for an integrated solution. It is necessary to pursue the integrated concept right from the beginning of the planning phase in order to achieve a high reliability from a production line with SMIF automation. The main requirement of the philosophy is to provide process tools with integrated SMIF solutions. For the success of the project, process tools including SMIF and minienvironment components must be purchased. The main priority of a SMIF project is to discuss with tool vendors and SMIF/Minienvironment OEM vendors before purchasing the process equipment. This paper describes from experience the procedures, interfaces and requirements necessary to realize a SMIF manufacturing line with a high number of integrated SMIF process tool solutions.
{"title":"Experiences with SMIF-integration for semiconductor fabrication","authors":"B. Klumpp, J. Schliesser, O. Herzog, P. Staudt-Fischbach","doi":"10.1109/ASMC.1995.484409","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484409","url":null,"abstract":"SMIF technology for microelectronic production lines is being increasingly used worldwide. A crucial factor for an economical SMIF solution is the planning phase, where experience has shown that the general approach to the project must aim for an integrated solution. It is necessary to pursue the integrated concept right from the beginning of the planning phase in order to achieve a high reliability from a production line with SMIF automation. The main requirement of the philosophy is to provide process tools with integrated SMIF solutions. For the success of the project, process tools including SMIF and minienvironment components must be purchased. The main priority of a SMIF project is to discuss with tool vendors and SMIF/Minienvironment OEM vendors before purchasing the process equipment. This paper describes from experience the procedures, interfaces and requirements necessary to realize a SMIF manufacturing line with a high number of integrated SMIF process tool solutions.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"33 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132318188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484372
R. Abugov, X. J. Dietrich
In the competitive world of high performance microprocessors, time to market is of first priority, and extremely steep ramps in yield are critical to financial success. Such rapid increases in yield require rapid and accurate detection of problems in the manufacturing process. Classically, detection of process problems relies on the use of capability metrics, such as C/sub p/ and C/sub pk/. Such metrics are accurate if the design limits are absolutely precise but, in early stages of prototype production, this assumption is often not justified. In this paper, we define point and interval estimates for 'yield impact metrics'. Such metrics circumvent the lack of precise design limits by directly measuring the impact of process inaccuracy upon yield. Improvement of processes with high yield impacts results in maximal acceleration of the yield ramp. In addition, we demonstrate application of these metrics to a yield ramp of one of Digital Equipment's new microprocessors.
{"title":"A yield based replacement for capability indexes","authors":"R. Abugov, X. J. Dietrich","doi":"10.1109/ASMC.1995.484372","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484372","url":null,"abstract":"In the competitive world of high performance microprocessors, time to market is of first priority, and extremely steep ramps in yield are critical to financial success. Such rapid increases in yield require rapid and accurate detection of problems in the manufacturing process. Classically, detection of process problems relies on the use of capability metrics, such as C/sub p/ and C/sub pk/. Such metrics are accurate if the design limits are absolutely precise but, in early stages of prototype production, this assumption is often not justified. In this paper, we define point and interval estimates for 'yield impact metrics'. Such metrics circumvent the lack of precise design limits by directly measuring the impact of process inaccuracy upon yield. Improvement of processes with high yield impacts results in maximal acceleration of the yield ramp. In addition, we demonstrate application of these metrics to a yield ramp of one of Digital Equipment's new microprocessors.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125355298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484387
M. Sugimoto, H. Hamada
This paper describes a memory yield enhancement system that allows rapid determination of problematic wafer processing steps during mass production. Previously, we had developed an expert system that, in addition to generating the defect statistics, can quickly predict a fault's cause as well as the processing step with the high probability of being responsible for the cause with 40 seconds for a 16 M DRAM. The system discussed in this paper combines our expert system with a conventional, stand-alone cell-to-cell comparison-based wafer inspection tool via an innovative software link. Comparison of wafer mappings, produced independently by the expert system and the wafer inspection tool, enables fast confirmation of the expert system's predictions. As a result, a production engineer can quickly recognize the corrective action to take to prevent the recurrence of the defect for the process step concerned. Use of this system has allowed quick identification of the cause of actual low yield circumstances.
本文描述了一种存储器良率增强系统，该系统可以在批量生产过程中快速确定有问题的晶圆加工步骤。以前，我们开发了一个专家系统，除了生成缺陷统计数据外，还可以快速预测故障原因以及处理步骤，对于16 M DRAM，只需40秒就可以对原因负责。本文讨论的系统通过创新的软件链接将我们的专家系统与传统的、独立的基于单元间比较的晶圆检测工具相结合。由专家系统和晶圆检测工具独立生成的晶圆映射的比较，可以快速确认专家系统的预测。因此，生产工程师可以快速识别纠正措施，以防止有关工艺步骤的缺陷再次发生。使用该系统可以快速识别实际低产量情况的原因。
{"title":"Yield enhancement using a memory expert system linked to the wafer inspection tool","authors":"M. Sugimoto, H. Hamada","doi":"10.1109/ASMC.1995.484387","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484387","url":null,"abstract":"This paper describes a memory yield enhancement system that allows rapid determination of problematic wafer processing steps during mass production. Previously, we had developed an expert system that, in addition to generating the defect statistics, can quickly predict a fault's cause as well as the processing step with the high probability of being responsible for the cause with 40 seconds for a 16 M DRAM. The system discussed in this paper combines our expert system with a conventional, stand-alone cell-to-cell comparison-based wafer inspection tool via an innovative software link. Comparison of wafer mappings, produced independently by the expert system and the wafer inspection tool, enables fast confirmation of the expert system's predictions. As a result, a production engineer can quickly recognize the corrective action to take to prevent the recurrence of the defect for the process step concerned. Use of this system has allowed quick identification of the cause of actual low yield circumstances.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484350
N. Pierce, A. Yost
This paper presents a case study for the successful development and effective use of cycle time metrics for fabricating semiconductor wafers in a research and development (R&D) environment. The metrics include multiples of theoretical cycle time (MTCT), breakdown analysis of cycle time, and cumulative queue times of baseline processes. Each of these metrics was applied to equipment types, process recipes, and overall pilot line performance as well as to production areas such as Films, Implant, and Etch.
{"title":"Cycle time metrics for R&D semiconductor wafer fabrication","authors":"N. Pierce, A. Yost","doi":"10.1109/ASMC.1995.484350","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484350","url":null,"abstract":"This paper presents a case study for the successful development and effective use of cycle time metrics for fabricating semiconductor wafers in a research and development (R&D) environment. The metrics include multiples of theoretical cycle time (MTCT), breakdown analysis of cycle time, and cumulative queue times of baseline processes. Each of these metrics was applied to equipment types, process recipes, and overall pilot line performance as well as to production areas such as Films, Implant, and Etch.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122922876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484331
T. Winter, D. Colston, E. Mickler, R. Woodward, M. Kimmich, T. Green
An High Yield Technology model 70 in-situ particle monitor (ISPM) has been installed on the pumpline of a Novellus C1 WCVD process chamber in an effort to better characterize and control the particle performance of the chamber, especially as it pertains to gas phase nucleation (GPN) in the tool. GPN results when the SiH/sub 4/:WF/sub 6/ ratio exceeds 1:1 at the system operating pressure and temperature. During experimentation the GPN boundary conditions were identified and the factors which controlled the phenomena were explored. The ISPM was used to detect the occurrence of a GPN event. A good correlation between high ISPM counts and in-film particles was established. The ISPM was a crucial element in identifying process boundary conditions as they related to GPN; this in turn helped assure control of the process wafers. An additional effect was noted as relates to formation and deposition of the nucleation sites on the wafer. In a two wafer test GPN was purposely generated, with the ISPM detecting comparable levels of particles during the processing of both wafers; however, very few particles were detected on the first wafer whereas several hundred particles were detected on the second wafer. This effect has been attributed to thermophoretic effects protecting the first wafer, with the second wafer being contaminated before it was heated.
{"title":"ISPM characterization of gas phase nucleation in a Novellus C1 WCVD process chamber","authors":"T. Winter, D. Colston, E. Mickler, R. Woodward, M. Kimmich, T. Green","doi":"10.1109/ASMC.1995.484331","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484331","url":null,"abstract":"An High Yield Technology model 70 in-situ particle monitor (ISPM) has been installed on the pumpline of a Novellus C1 WCVD process chamber in an effort to better characterize and control the particle performance of the chamber, especially as it pertains to gas phase nucleation (GPN) in the tool. GPN results when the SiH/sub 4/:WF/sub 6/ ratio exceeds 1:1 at the system operating pressure and temperature. During experimentation the GPN boundary conditions were identified and the factors which controlled the phenomena were explored. The ISPM was used to detect the occurrence of a GPN event. A good correlation between high ISPM counts and in-film particles was established. The ISPM was a crucial element in identifying process boundary conditions as they related to GPN; this in turn helped assure control of the process wafers. An additional effect was noted as relates to formation and deposition of the nucleation sites on the wafer. In a two wafer test GPN was purposely generated, with the ISPM detecting comparable levels of particles during the processing of both wafers; however, very few particles were detected on the first wafer whereas several hundred particles were detected on the second wafer. This effect has been attributed to thermophoretic effects protecting the first wafer, with the second wafer being contaminated before it was heated.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132533476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484360
J. Maeritz, H. Moller, F.G. Bobel, D. Ritter, M. Weusthof, J. Holleman
Summary form only given. RTCVD-facilities aspire to be one of the most used production tools in high yield semiconductor manufacturing in the next years. To obtain best quality electronic devices with a great flexibility it is necessary to observe and control many process parameters. Temperature and film thickness are two of these quantities. Since RSPI is an established real time tool for in-situ temperature and film thickness evaluation at many wafer production facilities, the task was to extend its applicability to RTCVD-facilities. To overcome optical irradiation of RTP-sources infrared RSPI adaptions were made in the wavelength region of 1.5 /spl mu/m. The measurement equipment according to RTCVD-facilities is compared with the standard RSPI-setup. In this paper data of temperature and film growth measurements are presented in dependence of various material compositions and observation wavelength. It is shown that the lowest measurable temperature with a minimal resolution 1/spl deg/C is about 380/spl deg/C up to 450/spl deg/C depending on the wafer material and observation wavelength. Beyond temperature and film thickness evaluation we succeeded in the first temperature controlling during film with RSPI-methods at RTCVD-facilities. The paper also demonstrates growth rates of films are held much more constant with temperature control in comparison to deposition procedures without temperature control. Material compositions of the discussed data are Poly-Si on Si; Si on Ge; SiN on Si and so on.
{"title":"Temperature controlling with reflexion supported pyrometric interferometry (RSPI) at rapid thermal chemical vapor deposition-facilities (RTCVD)","authors":"J. Maeritz, H. Moller, F.G. Bobel, D. Ritter, M. Weusthof, J. Holleman","doi":"10.1109/ASMC.1995.484360","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484360","url":null,"abstract":"Summary form only given. RTCVD-facilities aspire to be one of the most used production tools in high yield semiconductor manufacturing in the next years. To obtain best quality electronic devices with a great flexibility it is necessary to observe and control many process parameters. Temperature and film thickness are two of these quantities. Since RSPI is an established real time tool for in-situ temperature and film thickness evaluation at many wafer production facilities, the task was to extend its applicability to RTCVD-facilities. To overcome optical irradiation of RTP-sources infrared RSPI adaptions were made in the wavelength region of 1.5 /spl mu/m. The measurement equipment according to RTCVD-facilities is compared with the standard RSPI-setup. In this paper data of temperature and film growth measurements are presented in dependence of various material compositions and observation wavelength. It is shown that the lowest measurable temperature with a minimal resolution 1/spl deg/C is about 380/spl deg/C up to 450/spl deg/C depending on the wafer material and observation wavelength. Beyond temperature and film thickness evaluation we succeeded in the first temperature controlling during film with RSPI-methods at RTCVD-facilities. The paper also demonstrates growth rates of films are held much more constant with temperature control in comparison to deposition procedures without temperature control. Material compositions of the discussed data are Poly-Si on Si; Si on Ge; SiN on Si and so on.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484342
G. Horner, M. Fung, R.L. Verkuil, T. G. Miller
The strict demands for wafer cleanliness and impurity elimination outlined in the Semiconductor Industry Association's Technology Roadmap require that new monitoring methods be developed for measurement of oxide contamination. A newly available technology is presented here that will help manufacturers achieve the goals of oxide contamination monitoring and feedforward control. The technique is based on the principles of capacitance-voltage (C-V) monitoring, but the measurements are performed in a noncontacting fashion, thus greatly speeding the return of information to the user.
{"title":"COS-based Q-V testing: in-line options for oxide charge monitoring","authors":"G. Horner, M. Fung, R.L. Verkuil, T. G. Miller","doi":"10.1109/ASMC.1995.484342","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484342","url":null,"abstract":"The strict demands for wafer cleanliness and impurity elimination outlined in the Semiconductor Industry Association's Technology Roadmap require that new monitoring methods be developed for measurement of oxide contamination. A newly available technology is presented here that will help manufacturers achieve the goals of oxide contamination monitoring and feedforward control. The technique is based on the principles of capacitance-voltage (C-V) monitoring, but the measurements are performed in a noncontacting fashion, thus greatly speeding the return of information to the user.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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