Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484368
A. Sukhoparov
The post Soviet Union development of the enterprises of the Russian electronics industry is resembling the personality development model. Having recognized their lack of competence, Russian managers are now developing various ways to transform their enterprises. One of the ways is to transform, in several stages, the R&D department into specialized targeted groups and further create the modern SC manufacturing facilities on their basis.
{"title":"Current realities and future opportunities for Russia's semiconductor industry","authors":"A. Sukhoparov","doi":"10.1109/ASMC.1995.484368","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484368","url":null,"abstract":"The post Soviet Union development of the enterprises of the Russian electronics industry is resembling the personality development model. Having recognized their lack of competence, Russian managers are now developing various ways to transform their enterprises. One of the ways is to transform, in several stages, the R&D department into specialized targeted groups and further create the modern SC manufacturing facilities on their basis.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484396
S. Brown, P. Ackmann, V. Wenner, J. Lowell, W. Ostrout, C. Willson
In this paper we report on the application of optical surface photovoltage (SPV) to both quantify and qualify both surface and bulk effects of transition and alkaline metals deposited from photoresist in CZ P-type silicon. Using standard and specially prepared 1.2 /spl mu/ resist chemistry, we will demonstrate systematically that specific ions can affect surface charge and minority carrier lifetime. We will also show how the technique can be used for nondestructive, in-line assessment of resist-deposited contaminant metals.
本文报道了光学表面光电压(SPV)在czp型硅中沉积的过渡金属和碱性金属的表面和体效应的量化和定性应用。采用标准的和专门制备的1.2 /spl μ m /抗蚀剂化学方法，系统地论证了特定离子对表面电荷和少数载流子寿命的影响。我们还将展示如何将该技术用于非破坏性，在线评估电阻沉积的污染金属。
{"title":"Passive evaluation of surface and bulk ionic deposition from resist removal using surface photovoltage","authors":"S. Brown, P. Ackmann, V. Wenner, J. Lowell, W. Ostrout, C. Willson","doi":"10.1109/ASMC.1995.484396","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484396","url":null,"abstract":"In this paper we report on the application of optical surface photovoltage (SPV) to both quantify and qualify both surface and bulk effects of transition and alkaline metals deposited from photoresist in CZ P-type silicon. Using standard and specially prepared 1.2 /spl mu/ resist chemistry, we will demonstrate systematically that specific ions can affect surface charge and minority carrier lifetime. We will also show how the technique can be used for nondestructive, in-line assessment of resist-deposited contaminant metals.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128716432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484334
K. Mautz, R. Bloom
As capital requirements for new integrated circuit factories increase, cost of ownership for the wafer factory equipment becomes increasingly important. Utilization of a mix-and-match equipment strategy in lithography, combining critical and noncritical tools has been used as a technique to increase productivity. Despite the success of mix-and-match lithography strategies, the application of this strategy for etch tools has lagged. The requirements of the specific etch processes can be evaluated to determine the suitability of noncritical tool applications to meet the process requirements. Tool cost ratios and cost of ownership calculations are used to determine the potential savings in terms of capital outlays and wafer costs. It was found that potential savings of 10-26% could be achieved using the critical/noncritical etch tool selection strategy.
{"title":"Plasma etch tool selection criteria for minimizing cost of ownership","authors":"K. Mautz, R. Bloom","doi":"10.1109/ASMC.1995.484334","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484334","url":null,"abstract":"As capital requirements for new integrated circuit factories increase, cost of ownership for the wafer factory equipment becomes increasingly important. Utilization of a mix-and-match equipment strategy in lithography, combining critical and noncritical tools has been used as a technique to increase productivity. Despite the success of mix-and-match lithography strategies, the application of this strategy for etch tools has lagged. The requirements of the specific etch processes can be evaluated to determine the suitability of noncritical tool applications to meet the process requirements. Tool cost ratios and cost of ownership calculations are used to determine the potential savings in terms of capital outlays and wafer costs. It was found that potential savings of 10-26% could be achieved using the critical/noncritical etch tool selection strategy.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121875404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484355
M.B. Ferrara, K. Welch, L.D. Clementi, J. D. Hunt, S. Wolter, E.C. Bates
The ability to detect and classify material defects, such as epitaxial stacking faults, and pits in the surface region of silicon substrates is rapidly gaining importance as an additional wafer evaluation criterion. Traditionally, surface scanning inspection systems (SSIS) have been utilized to detect and quantify particulate contamination in process control applications. This study investigates the ability to detect and image these material defects using an enhanced SSIS. The imaging apparatus studied for this unique method operates concurrently with the conventional mode of operation for particle detection which relies on light scattering events. In the case of imaging material defects, a loss in the reflected light source beam intensity is measured. This technique, reconvergent specular detection (RSD), samples the reflected beam and is more commonly known as light channel detection. Stacking faults, pits, and slurry residue, common defect features on silicon, are examined in this study using the light channel detector. This work establishes that these types of defects are difficult to quantify when restricted to conventional detection methods. The light channel detection method, however, is capable of accurately imaging these defects according to size and shape. This paper highlights these results explains light channel phenomena in terms of detection theory and defect surface area. This novel imaging method offers a means of both detecting material defects and classifying them.
{"title":"Reconvergent specular detection of material defects on silicon","authors":"M.B. Ferrara, K. Welch, L.D. Clementi, J. D. Hunt, S. Wolter, E.C. Bates","doi":"10.1109/ASMC.1995.484355","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484355","url":null,"abstract":"The ability to detect and classify material defects, such as epitaxial stacking faults, and pits in the surface region of silicon substrates is rapidly gaining importance as an additional wafer evaluation criterion. Traditionally, surface scanning inspection systems (SSIS) have been utilized to detect and quantify particulate contamination in process control applications. This study investigates the ability to detect and image these material defects using an enhanced SSIS. The imaging apparatus studied for this unique method operates concurrently with the conventional mode of operation for particle detection which relies on light scattering events. In the case of imaging material defects, a loss in the reflected light source beam intensity is measured. This technique, reconvergent specular detection (RSD), samples the reflected beam and is more commonly known as light channel detection. Stacking faults, pits, and slurry residue, common defect features on silicon, are examined in this study using the light channel detector. This work establishes that these types of defects are difficult to quantify when restricted to conventional detection methods. The light channel detection method, however, is capable of accurately imaging these defects according to size and shape. This paper highlights these results explains light channel phenomena in terms of detection theory and defect surface area. This novel imaging method offers a means of both detecting material defects and classifying them.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"308 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114282530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484385
F. Lee, Ping Wang, R. Ceton, R. Goodner, M. Chan
This paper describes the yield enhancement strategies used in the startup of Motorola's MOS 12 fab, with the goal of establishing production capability in minimum time. This goal was achieved by implementing process qualification with real time in-line defect monitoring using a well characterized memory product. Wafer inspection and troubleshooting were facilitated by the acquisition of patterned wafer inspection tools employing several different defect detection technologies: pattern analysis, optical pattern filtering, and light scattering. The considerations for equipment startup are discussed, with emphasis on in-line inspection strategy and data analysis tools.
{"title":"Yield enhancement strategies for start-up of a high-volume 8-inch wafer fab","authors":"F. Lee, Ping Wang, R. Ceton, R. Goodner, M. Chan","doi":"10.1109/ASMC.1995.484385","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484385","url":null,"abstract":"This paper describes the yield enhancement strategies used in the startup of Motorola's MOS 12 fab, with the goal of establishing production capability in minimum time. This goal was achieved by implementing process qualification with real time in-line defect monitoring using a well characterized memory product. Wafer inspection and troubleshooting were facilitated by the acquisition of patterned wafer inspection tools employing several different defect detection technologies: pattern analysis, optical pattern filtering, and light scattering. The considerations for equipment startup are discussed, with emphasis on in-line inspection strategy and data analysis tools.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129617051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484345
P. Henshaw, S. Lis
The goal of this paper is to examine the economic impact of improved overlay during the lithography process. The motivation for this work is the development at SPARTA of an interferometer able to compensate directly for air turbulence. This improved interferometer will allow better stage positioning, lens and reticle characterization, and alignment of wafers during exposure. In this paper, we examine the effects of improved overlay on integrated circuit (IC) yield and the resulting increase in value to the IC manufacturer for present and future IC generations.
{"title":"Economic impact of a new interferometer providing improved overlay for advanced microlithography","authors":"P. Henshaw, S. Lis","doi":"10.1109/ASMC.1995.484345","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484345","url":null,"abstract":"The goal of this paper is to examine the economic impact of improved overlay during the lithography process. The motivation for this work is the development at SPARTA of an interferometer able to compensate directly for air turbulence. This improved interferometer will allow better stage positioning, lens and reticle characterization, and alignment of wafers during exposure. In this paper, we examine the effects of improved overlay on integrated circuit (IC) yield and the resulting increase in value to the IC manufacturer for present and future IC generations.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130598845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484327
S. D. Hossain, M. Paś, G. Miner, C. Cleavelin
The process and machine performance of an ion implantation anneal process performed using a Rapid Thermal Processing (RTP) system for 0.25 /spl mu/m technology are presented. As outlined in the 1994 Semiconductor Industry Association (SIA) National Technology Roadmap for Semiconductors, the 0.25 /spl mu/m devices will require junction depths of 50 to 120 nm and a surface concentration at channel of 1E18 atoms-cm/sup -3/. These requirements for junction depth and surface concentration can only be met by using an RTP for the ion implant anneal. This paper reviews the process performance of the anneal process in terms of sheet resistance, surface and bulk contamination. It also includes the results of an initial and final marathon to qualify the RTP for use in a manufacturing environment.
{"title":"Rapid thermal processing (RTP) applied to ion implant anneal for 0.25 /spl mu/m technology","authors":"S. D. Hossain, M. Paś, G. Miner, C. Cleavelin","doi":"10.1109/ASMC.1995.484327","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484327","url":null,"abstract":"The process and machine performance of an ion implantation anneal process performed using a Rapid Thermal Processing (RTP) system for 0.25 /spl mu/m technology are presented. As outlined in the 1994 Semiconductor Industry Association (SIA) National Technology Roadmap for Semiconductors, the 0.25 /spl mu/m devices will require junction depths of 50 to 120 nm and a surface concentration at channel of 1E18 atoms-cm/sup -3/. These requirements for junction depth and surface concentration can only be met by using an RTP for the ion implant anneal. This paper reviews the process performance of the anneal process in terms of sheet resistance, surface and bulk contamination. It also includes the results of an initial and final marathon to qualify the RTP for use in a manufacturing environment.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131200966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484366
S. Fine, A. D. Johnson, J. Langan, R. Pearce
Summary form only given. The storage of ultra-high purity (UHP) gases is a critical issue to the electronics industry. To prepare a storage vessel or delivery manifold for ultra-high purity gas service, all the atmospheric contaminants must be thoroughly removed from the system. Of these contaminants, atmospheric moisture is the most difficult to remove. It readily condenses on metal surfaces in multiple layers with a large heat adsorption. Typically, moisture is removed by purging or evacuation for long periods of time. In some cases it takes several weeks to adequately remove moisture from a delivery system. This is an expensive, time consuming process. Sometimes systems are heated to high temperature to reduce the time required to remove moisture. However, heating is not always practical, and it does nothing to prevent re-adsorption of water if the system is again exposed to ambient atmosphere. In many cases, moisture is the critical contaminant in the gas delivery system. This is especially true when the ultra-high purity gas is corrosive. Gases such as hydrogen chloride, hydrogen bromide, fluorine, tungsten hexafluoride and other halogen containing gases will severely corrode many metals if moisture is present. Corrosion of the storage vessel or delivery manifold can result in introduction of particle or gas-phase impurities into the ultra-high purity gas, or in extreme cases, result in failure of the system. Components such as valves, regulators, and mass now controllers are very susceptible to failure due to corrosion and frequently need to be replaced. This paper describes a new method for rapidly removing moisture from metal surfaces used in the packaging and delivery of high purity bulk and corrosive-speciality gases. Furthermore, the process passivates the metal by forming a hydrophobic surface that prevents water from readsorbing. Reagents of the type RsiXYZ where R is an alkyl group and at least one of X, Y, or Z is a hydrolyzable group are shown to enhance the removal of surface adsorbed moisture and gaseous product (HX). The HX by-product and unreacted RsiXYZ are rapidly and completely purged from the system. Since water is removed from the surface by chemical reaction rather than by simple purging, the initial dry down is faster. In addition to removing adsorbed water, the treatment incorporates a stable organosilicon group into the surface which greatly reduces the polar character associated with the OH terminated surface. The treated surface is hydrophobic inhibiting water from re-adsorbing during a subsequent moisture exposure. Stainless steel surfaces passivated in this manner are shown to have improved corrosion resistance compared to unpassivated stainless steel.
{"title":"A process for removing moisture from metal surfaces and inhibiting water from readsorbing using organosilanes","authors":"S. Fine, A. D. Johnson, J. Langan, R. Pearce","doi":"10.1109/ASMC.1995.484366","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484366","url":null,"abstract":"Summary form only given. The storage of ultra-high purity (UHP) gases is a critical issue to the electronics industry. To prepare a storage vessel or delivery manifold for ultra-high purity gas service, all the atmospheric contaminants must be thoroughly removed from the system. Of these contaminants, atmospheric moisture is the most difficult to remove. It readily condenses on metal surfaces in multiple layers with a large heat adsorption. Typically, moisture is removed by purging or evacuation for long periods of time. In some cases it takes several weeks to adequately remove moisture from a delivery system. This is an expensive, time consuming process. Sometimes systems are heated to high temperature to reduce the time required to remove moisture. However, heating is not always practical, and it does nothing to prevent re-adsorption of water if the system is again exposed to ambient atmosphere. In many cases, moisture is the critical contaminant in the gas delivery system. This is especially true when the ultra-high purity gas is corrosive. Gases such as hydrogen chloride, hydrogen bromide, fluorine, tungsten hexafluoride and other halogen containing gases will severely corrode many metals if moisture is present. Corrosion of the storage vessel or delivery manifold can result in introduction of particle or gas-phase impurities into the ultra-high purity gas, or in extreme cases, result in failure of the system. Components such as valves, regulators, and mass now controllers are very susceptible to failure due to corrosion and frequently need to be replaced. This paper describes a new method for rapidly removing moisture from metal surfaces used in the packaging and delivery of high purity bulk and corrosive-speciality gases. Furthermore, the process passivates the metal by forming a hydrophobic surface that prevents water from readsorbing. Reagents of the type RsiXYZ where R is an alkyl group and at least one of X, Y, or Z is a hydrolyzable group are shown to enhance the removal of surface adsorbed moisture and gaseous product (HX). The HX by-product and unreacted RsiXYZ are rapidly and completely purged from the system. Since water is removed from the surface by chemical reaction rather than by simple purging, the initial dry down is faster. In addition to removing adsorbed water, the treatment incorporates a stable organosilicon group into the surface which greatly reduces the polar character associated with the OH terminated surface. The treated surface is hydrophobic inhibiting water from re-adsorbing during a subsequent moisture exposure. Stainless steel surfaces passivated in this manner are shown to have improved corrosion resistance compared to unpassivated stainless steel.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123231870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484376
S. Saha, C. Kuppuswamy, J. Kraus
Intel Corporation has typically increased factory output by either adding more bottleneck equipment and/or improving equipment utilization. Utilization improvements were achieved by improving availability while maintaining the same or lower gap between availability and utilization. Typical availability improvement projects would require hardware changes (e.g. faster robots, faster pumps) or process changes, both of which have some level of technology risks. Lower risks from procedural changes make it an attractive alternate path for improvements. The seed idea for this program came from another Intel Fab experience which showed that right after a scheduled PM, the unscheduled downtimes would, immediately following a PM, almost double the baseline preceding the PM. This pointed to an opportunity to understand the PM content and its relationships to the equipment reliability since the experience indicated that, during every PM some "damage" was being done to the equipment which subsequently caused the post-PM failures. Since most of the improvements came from "procedural" improvements, this methodology has the added benefits of being "low risk". The "Indy 500" Team was formed in response to the low reliability of a tool that was factory output constraints. The Team consisted of all technicians from all shifts to improve teamwork, communication and training.
{"title":"PM effectiveness as a high leverage output improvement methodology","authors":"S. Saha, C. Kuppuswamy, J. Kraus","doi":"10.1109/ASMC.1995.484376","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484376","url":null,"abstract":"Intel Corporation has typically increased factory output by either adding more bottleneck equipment and/or improving equipment utilization. Utilization improvements were achieved by improving availability while maintaining the same or lower gap between availability and utilization. Typical availability improvement projects would require hardware changes (e.g. faster robots, faster pumps) or process changes, both of which have some level of technology risks. Lower risks from procedural changes make it an attractive alternate path for improvements. The seed idea for this program came from another Intel Fab experience which showed that right after a scheduled PM, the unscheduled downtimes would, immediately following a PM, almost double the baseline preceding the PM. This pointed to an opportunity to understand the PM content and its relationships to the equipment reliability since the experience indicated that, during every PM some \"damage\" was being done to the equipment which subsequently caused the post-PM failures. Since most of the improvements came from \"procedural\" improvements, this methodology has the added benefits of being \"low risk\". The \"Indy 500\" Team was formed in response to the low reliability of a tool that was factory output constraints. The Team consisted of all technicians from all shifts to improve teamwork, communication and training.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123682462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-11-13DOI: 10.1109/ASMC.1995.484328
A. Berti, E.A. Bonner
To accommodate the decreasing gate oxide thickness associated with Digital's new 0.5 /spl mu/m technology, the hardware for the pre-metallization sputter etches was retrofitted to reduce plasma damage. This change consisted of replacing the triode sputtering chambers in five sputtering tools with inductively coupled plasma sources. The new hardware not only had to be fully characterized and optimized, but required another climb up the manufacturability learning curve for particulate control and maintainability. Over a year and a half period, new procedures to improve availability were implemented resulting in a 9,000 wafer increase in the number of wafers run between etch chambers preventative maintenance intervals.
{"title":"Manufacturability improvements of inductively coupled plasma etch chambers in PVD tools","authors":"A. Berti, E.A. Bonner","doi":"10.1109/ASMC.1995.484328","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484328","url":null,"abstract":"To accommodate the decreasing gate oxide thickness associated with Digital's new 0.5 /spl mu/m technology, the hardware for the pre-metallization sputter etches was retrofitted to reduce plasma damage. This change consisted of replacing the triode sputtering chambers in five sputtering tools with inductively coupled plasma sources. The new hardware not only had to be fully characterized and optimized, but required another climb up the manufacturability learning curve for particulate control and maintainability. Over a year and a half period, new procedures to improve availability were implemented resulting in a 9,000 wafer increase in the number of wafers run between etch chambers preventative maintenance intervals.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128140534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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