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Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop最新文献

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Improving manufacturing performance at the Rochester Institute of Technology integrated circuit factory 改善罗彻斯特理工学院集成电路工厂的制造性能
Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484404
L. Fuller, K. Hirschman
The Integrated circuit Factory at RIT has realized much success in improving manufacturing performance and advancement toward six-sigma process capability goals. The Factory is comprised of approximately 20 graduate and undergraduate students in microelectronic engineering. Customers include a small number of companies and other universities in addition to faculty members and graduate students in electrical, microelectronic, and computer engineering at RIT. Products mostly consist of analog and digital CMOS integrated circuits fabricated in a P-well CMOS process. The factory maintains a work-in-progress (WIP) level of around 5 lots (50 wafers) and has a throughput of approximately 50 lots per year, with an average lot cycle time of approximately 1 month. The university IC facility is very dynamic in that the operators, equipment, and processes are constantly changing, The process capability baseline has been obtained from data collected for the past several years of student-run factory operation. A methodology to improve the quality of the student-run factory was implemented and is described in detail, The baseline study found that none of processes had process capability (Cpk) greater than one (3 sigma). However, manufacturing performance and product quality has been greatly improved by implementing the following set of tools: computer integrated manufacturing (CIM); total quality management (TQM) methodology; statistical process control (SPC); and "six-sigma" process capability analysis. Today several processes show Cpk>1. The student run integrated circuit factory at RIT has made significant progress toward achieving six-sigma manufacturing goals.
RIT的集成电路工厂在提高制造性能和向六西格玛过程能力目标迈进方面取得了很大的成功。该工厂由大约20名微电子工程专业的研究生和本科生组成。客户包括少数公司和其他大学,以及RIT电气、微电子和计算机工程专业的教师和研究生。产品主要由p阱CMOS工艺制造的模拟和数字CMOS集成电路组成。工厂保持在制品(WIP)水平约为5批次(50片晶圆),年产量约为50批次,平均批次周期约为1个月。大学的集成电路设施非常动态,操作员、设备和工艺都在不断变化,工艺能力基线是根据过去几年学生运营工厂收集的数据获得的。实施并详细描述了提高学生工厂质量的方法。基线研究发现,没有一个过程的过程能力(Cpk)大于1(3西格玛)。然而,通过实施以下一套工具,制造性能和产品质量得到了极大的提高:计算机集成制造(CIM);全面质量管理(TQM)方法;统计过程控制;以及“六西格玛”过程能力分析。今天有几个进程显示Cpk>1。RIT学生运营的集成电路工厂在实现六西格玛生产目标方面取得了重大进展。
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引用次数: 2
Facility fluids cost models 设施流体成本模型
Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484336
N. Patel, T. Boswell, T. Nelson
As a part of a SEMATECH project to improve the cost performance of semiconductor facility fluid systems, cost models have been developed in Microsoft Excel for gas chemicals, and ultra pure water (UPW) systems. These cost models are designed to permit cost analysis associated with the acquisition, use, and maintenance of fluid systems as well as cost comparisons of various fluid supply and distribution methods using a consistent costing methodology. The system attributes to be input in the model include the flowrate, and maintenance/reliability data. The subsystem attributes to be input in the model include the capital costs, leased equipment costs, utility usage, labor requirements, and other operating costs. Based on these inputs, the total capital and operating costs are calculated for a fluid system and ten year cost analysis is performed. The output is reported in terms of cost per unit volume.
作为SEMATECH项目的一部分,为了提高半导体设施流体系统的成本性能,在Microsoft Excel中开发了气体化学品和超纯水(UPW)系统的成本模型。这些成本模型的目的是为了分析与流体系统的获取、使用和维护相关的成本,以及使用一致的成本计算方法对各种流体供应和分配方法进行成本比较。要在模型中输入的系统属性包括流量和维护/可靠性数据。在模型中输入的子系统属性包括资本成本、租用设备成本、效用使用、劳动力需求和其他操作成本。基于这些输入,计算流体系统的总资本和运营成本,并进行十年成本分析。产量是以每单位产量的成本来报告的。
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引用次数: 1
Development of cost of ownership modeling at a semiconductor production facility 开发半导体生产设施的拥有成本模型
Pub Date : 1995-09-19 DOI: 10.1109/ASMC.1995.484362
Raul Nañez, A. Iturralde
Current trends in semiconductor manufacturing place a large emphasis on monitoring and/or controlling costs. One of the tools used in this effort is cost of ownership modeling. Cost of ownership provides a method to monitor and control costs, evaluate projects, and gain a better understanding into the manufacturing process. From the previous literature on the subject, models can range from very simple to very complex. The need for complexity in this type of model must be evaluated with respect to the actual level of accuracy required. Quality of the data obtained is very important as inaccurate information can lead to potential misuse. From past experience, data collection for modeling can range from being easily accessible to very obscure. In the search for data, various departments such as finance, engineering, facilities, production, and many others must be consulted. The value of the information obtained versus the cost involved in obtaining this information must also be evaluated. In this paper, the development of a cost of ownership model is outlined with the emphasis being placed on the desired goals, the methods used, the sources and manipulation of the data, and a practical example. Future applications of cost of ownership modeling are also discussed as well as integration into a semiconductor production facility.
目前半导体制造业的趋势非常强调监控和/或控制成本。在此工作中使用的工具之一是所有权成本建模。拥有成本提供了一种监测和控制成本、评估项目以及更好地了解制造过程的方法。从之前关于该主题的文献来看,模型可以从非常简单到非常复杂。在这种类型的模型中,对复杂性的需求必须根据所需的实际精度水平进行评估。获得的数据质量非常重要,因为不准确的信息可能导致潜在的误用。从过去的经验来看,用于建模的数据收集可能很容易获得,也可能非常模糊。在查找数据时,必须咨询财务、工程、设施、生产等各个部门。还必须评估所获得的信息的价值与获取这些信息所涉及的成本。在本文中,概述了拥有成本模型的发展,重点放在预期目标、使用的方法、数据的来源和操作以及一个实际示例上。本文还讨论了拥有成本建模的未来应用以及集成到半导体生产设施中的情况。
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引用次数: 6
Development of an optimal inspection strategy for chemical mechanical polished (CMP) wafers 化学机械抛光(CMP)晶圆最优检测策略的开发
Pub Date : 1900-01-01 DOI: 10.1109/ASMC.1995.484406
R. Sacco, R. Cappel
Summary form only given. This paper details the path taken to develop an optimal inspection strategy for monitoring defect levels from a CMP process. The relative unpredictability of this process can cause thickness variations across a wafer. These variations make many conventional inspection techniques unreliable. The objective of this study is to analyze the validity of using: current inspection techniques, such as laser scattering and image processing tools; new inspection techniques, such as Perspective Darkfield imaging, circular polarization, low oblique laser scattering and new imaging techniques using high Numerical Aperture objectives with various magnification changers; modifications of current techniques. The results of these tests will be compiled and analyzed to determine if current inspection techniques can be used effectively within the process flow or if new inspection techniques must be incorporated.
只提供摘要形式。本文详细介绍了从CMP过程中为监视缺陷水平而开发最佳检查策略的路径。这一过程的相对不可预测性会导致晶圆片上的厚度变化。这些变化使得许多传统的检测技术不可靠。本研究的目的是分析使用当前检测技术的有效性,如激光散射和图像处理工具;新的检测技术,如透视暗场成像、圆偏振成像、低斜激光散射成像和采用不同放大倍数的大数值孔径物镜成像技术;对现有技术的改进。这些测试的结果将被汇编和分析,以确定当前的检测技术是否可以在工艺流程中有效地使用,或者是否必须纳入新的检测技术。
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引用次数: 0
期刊
Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop
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