Using memory models in a hardware-assisted acceleration/emulation environment, as contrasted with a software simulation environment, is often infused with some very specific problems. This paper describes a novel, yet reliable, methodology to capture the essential functionalities and timings, from a chip designer's perspective, of commonly used embedded memories. The captured data is placed in a structural template for creating a knowledge base, which is transformed into targeted hardware-ready memories. A testbench is also created to verify the new models against the original behavioral models. This methodology has been used for years in many real design projects with great success.
{"title":"A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models","authors":"P. Cheng","doi":"10.1109/ISQED.2008.35","DOIUrl":"https://doi.org/10.1109/ISQED.2008.35","url":null,"abstract":"Using memory models in a hardware-assisted acceleration/emulation environment, as contrasted with a software simulation environment, is often infused with some very specific problems. This paper describes a novel, yet reliable, methodology to capture the essential functionalities and timings, from a chip designer's perspective, of commonly used embedded memories. The captured data is placed in a structural template for creating a knowledge base, which is transformed into targeted hardware-ready memories. A testbench is also created to verify the new models against the original behavioral models. This methodology has been used for years in many real design projects with great success.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"449 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123385277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a supervised learning based dynamic power management (DPM) framework for a multicore processor, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the state of service queue occupancy and the task arrival rate) and then uses this predicted state to look up the optimal power management action from a pre-computed policy lookup table. The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce overhead of the PM which has to recurrently determine and issue voltage-frequency setting commands to each processor core in the system. Experimental results reveal that the proposed Bayesian classification based DPM technique ensures system-wide energy savings under rapidly and widely varying workloads.
{"title":"Improving the Efficiency of Power Management Techniques by Using Bayesian Classification","authors":"Hwisung Jung, Massoud Pedram","doi":"10.1109/ISQED.2008.133","DOIUrl":"https://doi.org/10.1109/ISQED.2008.133","url":null,"abstract":"This paper presents a supervised learning based dynamic power management (DPM) framework for a multicore processor, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the state of service queue occupancy and the task arrival rate) and then uses this predicted state to look up the optimal power management action from a pre-computed policy lookup table. The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce overhead of the PM which has to recurrently determine and issue voltage-frequency setting commands to each processor core in the system. Experimental results reveal that the proposed Bayesian classification based DPM technique ensures system-wide energy savings under rapidly and widely varying workloads.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121232108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of ultra deep-submicron (UDSM) regime of integrated circuits, the issues with circuit marginality related transient failures are on the rise. An example of such failures is the thermal hotspot-induced ones, which are common when a particular functional unit experiences high switching activity for a considerable duration. In this paper, we propose an on-line hotspot-induced transient failure testing scheme using the built-in self-test (BlST)-based approach which accurately distinguishes such a transient failure from a hard fail and greatly reduces the test cost by dissociating a tester from the test process. We apply the principle of Fmax testing based on frequency shmoo to obtain the maximum safe operating frequency for individual functional units in a chip. We also propose a DFT scheme to characterize the impact of a "hot" unit on its neighborhood and also the influence of a "hot" neighborhood on an otherwise "cold" unit in the reverse way. Thus the proposed architecture extends the capability of the conventional BIST to test a certain class of circuit marginality related transient failures with a very low hardware overhead.
{"title":"A Built-in Test and Characterization Method for Circuit Marginality Related Failures","authors":"A. Sanyal, S. Kundu","doi":"10.1109/ISQED.2008.51","DOIUrl":"https://doi.org/10.1109/ISQED.2008.51","url":null,"abstract":"With the advent of ultra deep-submicron (UDSM) regime of integrated circuits, the issues with circuit marginality related transient failures are on the rise. An example of such failures is the thermal hotspot-induced ones, which are common when a particular functional unit experiences high switching activity for a considerable duration. In this paper, we propose an on-line hotspot-induced transient failure testing scheme using the built-in self-test (BlST)-based approach which accurately distinguishes such a transient failure from a hard fail and greatly reduces the test cost by dissociating a tester from the test process. We apply the principle of Fmax testing based on frequency shmoo to obtain the maximum safe operating frequency for individual functional units in a chip. We also propose a DFT scheme to characterize the impact of a \"hot\" unit on its neighborhood and also the influence of a \"hot\" neighborhood on an otherwise \"cold\" unit in the reverse way. Thus the proposed architecture extends the capability of the conventional BIST to test a certain class of circuit marginality related transient failures with a very low hardware overhead.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With scaling technologies, process variations have increased significantly. This has led to deviations in analog performance from their expected values. Performance macromodeling aids in reduction of synthesis time by removing the simulation overhead. In this work, we develop a novel spline based center and range method (SCRM) for process variation aware performance macro-modeling (VAPMAC) which works on interval valued data. Experiments demonstrate around 200K times computational time advantage using VAPMAC generated macromodels over SPICE Monte Carlo simulation. The results also demonstrate less than 10% loss in accuracy in computing the performance bounds using the macromodels compared to the SPICE simulations.
{"title":"Variation Aware Spline Center and Range Modeling for Analog Circuit Performance","authors":"Shubhankar Basu, Balaji Kommineni, R. Vemuri","doi":"10.1109/ISQED.2008.118","DOIUrl":"https://doi.org/10.1109/ISQED.2008.118","url":null,"abstract":"With scaling technologies, process variations have increased significantly. This has led to deviations in analog performance from their expected values. Performance macromodeling aids in reduction of synthesis time by removing the simulation overhead. In this work, we develop a novel spline based center and range method (SCRM) for process variation aware performance macro-modeling (VAPMAC) which works on interval valued data. Experiments demonstrate around 200K times computational time advantage using VAPMAC generated macromodels over SPICE Monte Carlo simulation. The results also demonstrate less than 10% loss in accuracy in computing the performance bounds using the macromodels compared to the SPICE simulations.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the number of transistors on a chip begins to exceed 1 billion and their sensitivity to defects begins to degrade overall yield, it will be mandatory to assign a portion of the transistors for the purposes of built-in- self-test (BIST) and built-in-self-repair (BISR) as part of the supporting circuitry. Here, we focus on the self-test and self-repair of flip-flops (FF's), and their associated interconnect, using spare FF's to replace faulty ones. We describe our method to determine the number of spares based on delay and yield analysis. Using these results, we partition the flip-flops in a sequential design to improve the yield while keeping the delay and area overhead low. Next, we apply this redundancy approach only to non-critical paths in the circuit so that no timing penalty is incurred, and find that it can still provide significant improvement in the overall yield. A number of sequential benchmark circuits from ITC '99 are compared with and without redundant flip-flops, and also with and without partitioning. The total area overhead of our method is 8% on average while improving the yield by 6-29% and incurring no timing penalty.
{"title":"Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits","authors":"Uthman Alsaiari, R. Saleh","doi":"10.1109/ISQED.2008.143","DOIUrl":"https://doi.org/10.1109/ISQED.2008.143","url":null,"abstract":"As the number of transistors on a chip begins to exceed 1 billion and their sensitivity to defects begins to degrade overall yield, it will be mandatory to assign a portion of the transistors for the purposes of built-in- self-test (BIST) and built-in-self-repair (BISR) as part of the supporting circuitry. Here, we focus on the self-test and self-repair of flip-flops (FF's), and their associated interconnect, using spare FF's to replace faulty ones. We describe our method to determine the number of spares based on delay and yield analysis. Using these results, we partition the flip-flops in a sequential design to improve the yield while keeping the delay and area overhead low. Next, we apply this redundancy approach only to non-critical paths in the circuit so that no timing penalty is incurred, and find that it can still provide significant improvement in the overall yield. A number of sequential benchmark circuits from ITC '99 are compared with and without redundant flip-flops, and also with and without partitioning. The total area overhead of our method is 8% on average while improving the yield by 6-29% and incurring no timing penalty.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Sellier, J. Portal, B. Borot, S. Colquhoun, R. Ferrant, F. Boeuf, A. Farcy
The main goal of this paper is to study the delay evolution for future technology nodes (32 nm and beyond) using electrical circuit predictive simulations. With this aim, two SPICE predictive models, directly based on ITRS data, are developed for devices and for interconnect respectively. The predictive spice models generation is presented and validated versus 45 nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that the critical interconnect length should be in the order of 10 mum for the 2020 generation. Moreover, in forthcoming technologies, driver resizing and systematic buffer insertion will no longer be sufficient to systematically limit wire delay increase.
{"title":"Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework","authors":"M. Sellier, J. Portal, B. Borot, S. Colquhoun, R. Ferrant, F. Boeuf, A. Farcy","doi":"10.1109/ISQED.2008.137","DOIUrl":"https://doi.org/10.1109/ISQED.2008.137","url":null,"abstract":"The main goal of this paper is to study the delay evolution for future technology nodes (32 nm and beyond) using electrical circuit predictive simulations. With this aim, two SPICE predictive models, directly based on ITRS data, are developed for devices and for interconnect respectively. The predictive spice models generation is presented and validated versus 45 nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that the critical interconnect length should be in the order of 10 mum for the 2020 generation. Moreover, in forthcoming technologies, driver resizing and systematic buffer insertion will no longer be sufficient to systematically limit wire delay increase.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131363339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and derive the rational approximate with the help of vector fitting [9]. There are two aspects that contribute to the time efficiency of the method. One is CSAV solves the state equation only on selected frequency points, which significantly reduce the amount of time for equation solving. The other is CSAV performs vector fitting and waveform recovery only on user specified nodes, which save the unnecessary computation on the nodes which are not concerned by user. The complexity of our method is O( lceillg fmaxrceilNalpha + lceillg fmaxrceil 2NaNout), where fmax is proportional to the knee frequencyquency of input signal, N is the node number of the circuit, a is a constant around 1.3, Na is the order of approximation and Nout is the number of output nodes. Our experimental results show that compared with Hspice, CSAV achieves speed-up up to 35 times while the error is only 1%. Moreover, computational saving of CSAV grows with circuit size, which makes this method especially promising for large cases.
{"title":"Clock Skew Analysis via Vector Fitting in Frequency Domain","authors":"Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng","doi":"10.1109/ISQED.2008.67","DOIUrl":"https://doi.org/10.1109/ISQED.2008.67","url":null,"abstract":"An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and derive the rational approximate with the help of vector fitting [9]. There are two aspects that contribute to the time efficiency of the method. One is CSAV solves the state equation only on selected frequency points, which significantly reduce the amount of time for equation solving. The other is CSAV performs vector fitting and waveform recovery only on user specified nodes, which save the unnecessary computation on the nodes which are not concerned by user. The complexity of our method is O( lceillg fmaxrceilNalpha + lceillg fmaxrceil 2NaNout), where fmax is proportional to the knee frequencyquency of input signal, N is the node number of the circuit, a is a constant around 1.3, Na is the order of approximation and Nout is the number of output nodes. Our experimental results show that compared with Hspice, CSAV achieves speed-up up to 35 times while the error is only 1%. Moreover, computational saving of CSAV grows with circuit size, which makes this method especially promising for large cases.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131927799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, C. C. Chen
SSTA requires accurate statistical distribution models of non-Gaussian random variables of process parameters and timing variables. Traditional quadratic Gaussian model has been shown to have some serious limitations. In particular, it limits the range of skewness that can be modeled and it can not model the kurtosis. In this paper, we presented complex-coefficient quadratic Gaussian polynomial model and higher order Gaussian polynomial model to resolve these difficulties. Experimental results show how our methods and new algorithms expose some enhancements in both accuracy and versatility.
{"title":"Process-Variation Statistical Modeling for VLSI Timing Analysis","authors":"Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, C. C. Chen","doi":"10.1109/ISQED.2008.66","DOIUrl":"https://doi.org/10.1109/ISQED.2008.66","url":null,"abstract":"SSTA requires accurate statistical distribution models of non-Gaussian random variables of process parameters and timing variables. Traditional quadratic Gaussian model has been shown to have some serious limitations. In particular, it limits the range of skewness that can be modeled and it can not model the kurtosis. In this paper, we presented complex-coefficient quadratic Gaussian polynomial model and higher order Gaussian polynomial model to resolve these difficulties. Experimental results show how our methods and new algorithms expose some enhancements in both accuracy and versatility.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As processes shrink, the on-chip variability grows and this variation causes clock skew to rapidly consume a larger-and-larger percentage of the clock period. New techniques to reduce skew are required, but post-silicon clock adjustments will still be necessary to compensate for intra-die PVT variations. A relatively new technique for skew reduction, called Single-Edge Clocking (SEC), focuses clock buffer design on the critical edge by using alternating strong pull-up and strong pull-down buffers. In this paper, a new digitally-tuned buffer for SEC clock networks is presented. It is based on a single-sided starved inverter configuration and is tuned using a 3-bit thermometer code. Sizing issues and skew reduction achievable in the presence of PVT variations are presented. The overhead in terms of layout area and current consumption for this new tunable buffer is only a small fraction of other tunable buffer designs.
{"title":"A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks","authors":"Jeff Mueller, R. Saleh","doi":"10.1109/ISQED.2008.47","DOIUrl":"https://doi.org/10.1109/ISQED.2008.47","url":null,"abstract":"As processes shrink, the on-chip variability grows and this variation causes clock skew to rapidly consume a larger-and-larger percentage of the clock period. New techniques to reduce skew are required, but post-silicon clock adjustments will still be necessary to compensate for intra-die PVT variations. A relatively new technique for skew reduction, called Single-Edge Clocking (SEC), focuses clock buffer design on the critical edge by using alternating strong pull-up and strong pull-down buffers. In this paper, a new digitally-tuned buffer for SEC clock networks is presented. It is based on a single-sided starved inverter configuration and is tuned using a 3-bit thermometer code. Sizing issues and skew reduction achievable in the presence of PVT variations are presented. The overhead in terms of layout area and current consumption for this new tunable buffer is only a small fraction of other tunable buffer designs.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131743034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Detecting and correcting errors in logic circuits is much more difficult than in memories. While concurrent error detection and correction mechanisms can be efficiently incorporated in memories due to their regular structure, logic circuits present a much greater challenge because of their irregular structure. One approach to handle the problems arising due to soft errors is to detect the errors using a concurrent error detection (CED) circuitry that monitors the circuit output for the occurrence of an error. Once the error is detected the system can recover and hence prevent a failure. While operating in an environment with high soft error rate and for systems with a stringent reliability and availability requirement, error detection alone may not be sufficient. While triple modular redundancy (TMR) can mask all single faults, the overhead can be unacceptably high for the targeted applications. This paper presents a low-overhead non-intrusive technique to detect and correct the most likely soft errors using customized ad-hoc error detecting and correcting (EDAC) linear block codes. Employing the proposed EDAC scheme can dramatically reduce the failure rate and increase the mean time to failure (MTTF) for logic circuits with limited overhead. For certain types of applications e.g., network servers, query servers, etc., with high availability and low cost requirements, the proposed approach could be very useful. The linearity property of the codes allows for efficient synthesis of the parity prediction logic. The experimental results demonstrate the effectiveness of the proposed scheme.
{"title":"Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes","authors":"Avijit Dutta, A. Jas","doi":"10.1109/ISQED.2008.56","DOIUrl":"https://doi.org/10.1109/ISQED.2008.56","url":null,"abstract":"Detecting and correcting errors in logic circuits is much more difficult than in memories. While concurrent error detection and correction mechanisms can be efficiently incorporated in memories due to their regular structure, logic circuits present a much greater challenge because of their irregular structure. One approach to handle the problems arising due to soft errors is to detect the errors using a concurrent error detection (CED) circuitry that monitors the circuit output for the occurrence of an error. Once the error is detected the system can recover and hence prevent a failure. While operating in an environment with high soft error rate and for systems with a stringent reliability and availability requirement, error detection alone may not be sufficient. While triple modular redundancy (TMR) can mask all single faults, the overhead can be unacceptably high for the targeted applications. This paper presents a low-overhead non-intrusive technique to detect and correct the most likely soft errors using customized ad-hoc error detecting and correcting (EDAC) linear block codes. Employing the proposed EDAC scheme can dramatically reduce the failure rate and increase the mean time to failure (MTTF) for logic circuits with limited overhead. For certain types of applications e.g., network servers, query servers, etc., with high availability and low cost requirements, the proposed approach could be very useful. The linearity property of the codes allows for efficient synthesis of the parity prediction logic. The experimental results demonstrate the effectiveness of the proposed scheme.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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