Mark Lysinger, F. Jacquet, M. Zamanian, David McClure, P. Roche, Nihar Ranjan Sahoo, J. Russell
An eight megabit rad hard SRAM, implemented in 130 nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600 nA.
{"title":"A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS","authors":"Mark Lysinger, F. Jacquet, M. Zamanian, David McClure, P. Roche, Nihar Ranjan Sahoo, J. Russell","doi":"10.1109/ISQED.2008.81","DOIUrl":"https://doi.org/10.1109/ISQED.2008.81","url":null,"abstract":"An eight megabit rad hard SRAM, implemented in 130 nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600 nA.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129292121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-17DOI: 10.1109/ISQED.2008.4479754
J. Palma, C. Marcon, Fabiano Hessel, E. Bezerra, Guilherme Rohde, L. Azevedo, C. Reif, C. Metzler
This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.
{"title":"A Passive 915 MHz UHF RFID Tag","authors":"J. Palma, C. Marcon, Fabiano Hessel, E. Bezerra, Guilherme Rohde, L. Azevedo, C. Reif, C. Metzler","doi":"10.1109/ISQED.2008.4479754","DOIUrl":"https://doi.org/10.1109/ISQED.2008.4479754","url":null,"abstract":"This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128749383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Bhattacharya, S. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
Sub-wavelength lithography in modern fabrication processes has resulted in a tremendous increase in the number of design rules. Of these, the context dependent design rules are especially hard to adhere to during manual layout creation. Layout legalization or automatic correction of design rule violation, therefore, has attained prime importance. Layout legalization can be modeled as a modified layout compaction problem. Generation of constraints from a given layout is a crucial step in compaction. In this paper, we propose a systematic framework for constraint generation that identifies context dependent rules and ensures legal layout upon compaction. In addition, we suggest practical schemes for reducing the legalization problem size that results in subsequent efficient solution.
{"title":"On Efficient and Robust Constraint Generation for Practical Layout Legalization","authors":"S. Bhattacharya, S. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy","doi":"10.1109/ISQED.2008.115","DOIUrl":"https://doi.org/10.1109/ISQED.2008.115","url":null,"abstract":"Sub-wavelength lithography in modern fabrication processes has resulted in a tremendous increase in the number of design rules. Of these, the context dependent design rules are especially hard to adhere to during manual layout creation. Layout legalization or automatic correction of design rule violation, therefore, has attained prime importance. Layout legalization can be modeled as a modified layout compaction problem. Generation of constraints from a given layout is a crucial step in compaction. In this paper, we propose a systematic framework for constraint generation that identifies context dependent rules and ensures legal layout upon compaction. In addition, we suggest practical schemes for reducing the legalization problem size that results in subsequent efficient solution.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115586117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electrostatic discharge, the transfer of charge between bodies that alters device characteristics has become a major reliability concern in the semiconductor industry. Conventional approaches of using ESD testers to detect ESD defects are post-fabrication methods which leave narrow design time for ESD rectification. This paper discusses a CAD approach which captures ESD problems in the design phase enabling designers to build robust ESD structures. The discussed verification platform performs ESD simulations on the design and aids designers to locate and debug the potential ESD failure nodes in the circuit. This approach leads to robust ESD designs with minimal cycle-time and reduces silicon re-spins.
{"title":"XStatic: A Simulation Based ESD Verification and Debug Environment","authors":"Ganesh R. Shamnur, Rajesh R. Berigei","doi":"10.1109/ISQED.2008.32","DOIUrl":"https://doi.org/10.1109/ISQED.2008.32","url":null,"abstract":"Electrostatic discharge, the transfer of charge between bodies that alters device characteristics has become a major reliability concern in the semiconductor industry. Conventional approaches of using ESD testers to detect ESD defects are post-fabrication methods which leave narrow design time for ESD rectification. This paper discusses a CAD approach which captures ESD problems in the design phase enabling designers to build robust ESD structures. The discussed verification platform performs ESD simulations on the design and aids designers to locate and debug the potential ESD failure nodes in the circuit. This approach leads to robust ESD designs with minimal cycle-time and reduces silicon re-spins.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114733810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulation governed by the formulated Monte Carlo model. The Monte Carlo simulation is terminated when the predefined error with respect to the Monte Carlo model, under a specified confidence level, is achieved. We conduct the experiments on a set of ISCAS '85 and MCNC benchmarks. As compared with previous work, our approach more efficiently evaluates the testability with less error rate.
{"title":"A Statistic-Based Approach to Testability Analysis","authors":"C. Chiou, Chun-Yao Wang, Yung-Chih Chen","doi":"10.1109/ISQED.2008.89","DOIUrl":"https://doi.org/10.1109/ISQED.2008.89","url":null,"abstract":"This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulation governed by the formulated Monte Carlo model. The Monte Carlo simulation is terminated when the predefined error with respect to the Monte Carlo model, under a specified confidence level, is achieved. We conduct the experiments on a set of ISCAS '85 and MCNC benchmarks. As compared with previous work, our approach more efficiently evaluates the testability with less error rate.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115120166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.
{"title":"Two New Methods for Accurate Test Set Relaxation via Test Set Replacement","authors":"Stelios N. Neophytou, M. Michael","doi":"10.1109/ISQED.2008.149","DOIUrl":"https://doi.org/10.1109/ISQED.2008.149","url":null,"abstract":"This paper presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.
{"title":"High Resolution Read-Out Circuit for DNA Label-Free Detection System","authors":"D. Venuto, B. Riccò","doi":"10.1109/ISQED.2008.153","DOIUrl":"https://doi.org/10.1109/ISQED.2008.153","url":null,"abstract":"This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the past, it was possible to validate analog CMOS circuits through transistor-level (schematic netlist) simulation. As manufacturing processes grow in complexity, the ever-increasing amount of design-for-test/manufacturability/yield/quality (DFx) circuitry renders transistor-level simulation impractical; and digital behavioral simulation ignores crucial analog interactions. This paper presents a more robust and efficient methodology for pre-silicon validation of such mixed-signal circuits. We adopt a top-down strategy and model all blocks at the behavioral level. However, we also represent select analog blocks at the transistor level. This strategy precludes the need for what is currently a weakness in mixed-signal validation - equivalence checking between analog behavioral models and analog schematics. In addition, this strategy enables performance validation to be seamlessly integrated with functional validation. Further, by leveraging the industry standard languages of SPICE, System Verilog and Verilog-AMS, we are able to build and simulate all modeling and validation constructs with a single tool. On Intel's most recent test chip, our validation methodology found more bugs with fewer person-hours than previous attempts with purely digital or transistor-level validation.
{"title":"A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips","authors":"N. August","doi":"10.1109/ISQED.2008.40","DOIUrl":"https://doi.org/10.1109/ISQED.2008.40","url":null,"abstract":"In the past, it was possible to validate analog CMOS circuits through transistor-level (schematic netlist) simulation. As manufacturing processes grow in complexity, the ever-increasing amount of design-for-test/manufacturability/yield/quality (DFx) circuitry renders transistor-level simulation impractical; and digital behavioral simulation ignores crucial analog interactions. This paper presents a more robust and efficient methodology for pre-silicon validation of such mixed-signal circuits. We adopt a top-down strategy and model all blocks at the behavioral level. However, we also represent select analog blocks at the transistor level. This strategy precludes the need for what is currently a weakness in mixed-signal validation - equivalence checking between analog behavioral models and analog schematics. In addition, this strategy enables performance validation to be seamlessly integrated with functional validation. Further, by leveraging the industry standard languages of SPICE, System Verilog and Verilog-AMS, we are able to build and simulate all modeling and validation constructs with a single tool. On Intel's most recent test chip, our validation methodology found more bugs with fewer person-hours than previous attempts with purely digital or transistor-level validation.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"609 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131424503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded deterministic test is a manufacture test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli, inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low-cost testers for rapidly achieving high fault coverage, embedded deterministic test must consciously use the available tester channel bandwidth to ensure non-disruptive scaling to future devices of increased complexity. The focus of this paper is to show how exploitation of care bit clustering in a test set combined with a low cost implementation for on-chip decompressors based on seed borrowing, facilitates an increased utilization of the tester channel bandwidth, and hence improved compression of deterministic stimuli.
{"title":"Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing","authors":"A. Kinsman, N. Nicolici","doi":"10.1109/ISQED.2008.65","DOIUrl":"https://doi.org/10.1109/ISQED.2008.65","url":null,"abstract":"Embedded deterministic test is a manufacture test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli, inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low-cost testers for rapidly achieving high fault coverage, embedded deterministic test must consciously use the available tester channel bandwidth to ensure non-disruptive scaling to future devices of increased complexity. The focus of this paper is to show how exploitation of care bit clustering in a test set combined with a low cost implementation for on-chip decompressors based on seed borrowing, facilitates an increased utilization of the tester channel bandwidth, and hence improved compression of deterministic stimuli.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128324805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present the statistical SPICE models and associated corner models of passive devices (such as capacitors and resistors) in VLSI semiconductor technologies. The capacitor devices include decoupling capacitors, metal- insulator-metal capacitors (MIMCAPs), junction capacitors, MOS varactors, BEOL metal capacitors, etc. The resistor devices include diffused resistors, silicide blocked polysilicon resistors, BEOL resistors, etc. We present correct statistical models and optimal corner models, and discuss the correctness and goodness of various statistical models and corner models. We explicitly show the dependency of the corner model parameters on the device length/width. For a fixed device length and width, for the first time, we show the dependency of the corner model parameters on the frequency, and show that the skewing direction of some corner model parameters will change their signs when going from the low frequency region to the high frequency/RF region.
{"title":"Statistical Models and Frequency-Dependent Corner Models for Passive Devices","authors":"N. Lu","doi":"10.1109/ISQED.2008.125","DOIUrl":"https://doi.org/10.1109/ISQED.2008.125","url":null,"abstract":"We present the statistical SPICE models and associated corner models of passive devices (such as capacitors and resistors) in VLSI semiconductor technologies. The capacitor devices include decoupling capacitors, metal- insulator-metal capacitors (MIMCAPs), junction capacitors, MOS varactors, BEOL metal capacitors, etc. The resistor devices include diffused resistors, silicide blocked polysilicon resistors, BEOL resistors, etc. We present correct statistical models and optimal corner models, and discuss the correctness and goodness of various statistical models and corner models. We explicitly show the dependency of the corner model parameters on the device length/width. For a fixed device length and width, for the first time, we show the dependency of the corner model parameters on the frequency, and show that the skewing direction of some corner model parameters will change their signs when going from the low frequency region to the high frequency/RF region.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"347 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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