In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal behavior of the processor, specially when low- power techniques like power gating are applied to the individual cores. In this work, a load-balancing technique that provides low overhead in performance and energy with respect to the highest performance case, yet featuring a smooth temperature distribution close to the optimal scenario is presented. An uneven temperature distribution leads to thermal hot spots which affect both the reliability of the processor (by stressing some parts of the die more than others), and the cost of the processor (since the package has to be designed to handle the worst hot spot).
{"title":"A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors","authors":"E. Musoll","doi":"10.1109/ISQED.2008.41","DOIUrl":"https://doi.org/10.1109/ISQED.2008.41","url":null,"abstract":"In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal behavior of the processor, specially when low- power techniques like power gating are applied to the individual cores. In this work, a load-balancing technique that provides low overhead in performance and energy with respect to the highest performance case, yet featuring a smooth temperature distribution close to the optimal scenario is presented. An uneven temperature distribution leads to thermal hot spots which affect both the reliability of the processor (by stressing some parts of the die more than others), and the cost of the processor (since the package has to be designed to handle the worst hot spot).","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114427693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 4-bit flash ADC is investigated in presence of substrate noise generated by switching activities in digital blocks. The impact of noise is analyzed in different building blocks of the ADC and is measured experimentally using a high-speed ADC test block fabricated in a 0.18-mum SiGe BiCMOS process. Measurement results show that noise spikes in the substrate cause distortion in the prototype ADC and degrade its SNDR by 2 dB (10%) at noise frequencies above 200 MHz.
研究了一个4位闪存ADC在数字块中开关活动所产生的衬底噪声的存在。在ADC的不同构建模块中分析了噪声的影响，并使用以0.18 μ m SiGe BiCMOS工艺制作的高速ADC测试模块进行了实验测量。测量结果表明，在噪声频率高于200 MHz时，衬底中的噪声尖峰会导致原型ADC失真，使其SNDR降低2 dB(10%)。
{"title":"Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs","authors":"P. Nikaeen, B. Murmann, R. Dutton","doi":"10.1109/ISQED.2008.141","DOIUrl":"https://doi.org/10.1109/ISQED.2008.141","url":null,"abstract":"A 4-bit flash ADC is investigated in presence of substrate noise generated by switching activities in digital blocks. The impact of noise is analyzed in different building blocks of the ADC and is measured experimentally using a high-speed ADC test block fabricated in a 0.18-mum SiGe BiCMOS process. Measurement results show that noise spikes in the substrate cause distortion in the prototype ADC and degrade its SNDR by 2 dB (10%) at noise frequencies above 200 MHz.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124855835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost.
{"title":"Error Protected Data Bus Inversion Using Standard DRAM Components","authors":"M. Skerlj, P. Ienne","doi":"10.1109/ISQED.2008.74","DOIUrl":"https://doi.org/10.1109/ISQED.2008.74","url":null,"abstract":"Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"507 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Wang, K. Agarwal, S. Nassif, K. Nowka, D. Markovic
A new approach to analyze process variation through measured current variation is introduced. The methodology concludes with a simple and convenient posynomial model for random process variability to bridge the gap between existing statistical methods and circuit design. The model contains only design variables: transistor sizes W and L, and operating points Vgs and Vds. Modeling random process variability in this way allows for adaptability to optimization problems, time efficient methods for gathering statistical information in comparison to Monte Carlo, and an alternative equation for hand analysis.
{"title":"A Design Model for Random Process Variability","authors":"V. Wang, K. Agarwal, S. Nassif, K. Nowka, D. Markovic","doi":"10.1109/ISQED.2008.111","DOIUrl":"https://doi.org/10.1109/ISQED.2008.111","url":null,"abstract":"A new approach to analyze process variation through measured current variation is introduced. The methodology concludes with a simple and convenient posynomial model for random process variability to bridge the gap between existing statistical methods and circuit design. The model contains only design variables: transistor sizes W and L, and operating points Vgs and Vds. Modeling random process variability in this way allows for adaptability to optimization problems, time efficient methods for gathering statistical information in comparison to Monte Carlo, and an alternative equation for hand analysis.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124198549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the positive feedback loop between power grid Joule heating and the linear temperature dependence of resistivity, non-uniform temperature profiles on the power grid in high-performance IC influence the IR drop in the power grid. Lack of accurate evaluation of thermal effect on the IR drop in the power grid may lead to over-design; or worse, underestimates the IR drop due to increased local temperature. This paper presents a method to compute the temperature-dependent IR drop on the power grid extremely fast. We propose a novel thermal model and a mathematical formulation to compute the temperature profiles on the power grid efficiently. Compared to the traditional thermal lumped model, which gives a much larger thermal network than the original power grid (20 times more nodes), our model takes advantage of power grid properties, and reduces the size of the thermal equivalent network dramatically (only 13% of the size of the power grid). Iterative methods [16] are used to efficiently update the IR drops based on the new temperature profile. Experimental results show that without considering temperature impact, the worst IR drop analysis can have error up to 10%.
{"title":"Thermal-Aware IR Drop Analysis in Large Power Grid","authors":"Yu Zhong, Martin D. F. Wong","doi":"10.1109/ISQED.2008.57","DOIUrl":"https://doi.org/10.1109/ISQED.2008.57","url":null,"abstract":"Due to the positive feedback loop between power grid Joule heating and the linear temperature dependence of resistivity, non-uniform temperature profiles on the power grid in high-performance IC influence the IR drop in the power grid. Lack of accurate evaluation of thermal effect on the IR drop in the power grid may lead to over-design; or worse, underestimates the IR drop due to increased local temperature. This paper presents a method to compute the temperature-dependent IR drop on the power grid extremely fast. We propose a novel thermal model and a mathematical formulation to compute the temperature profiles on the power grid efficiently. Compared to the traditional thermal lumped model, which gives a much larger thermal network than the original power grid (20 times more nodes), our model takes advantage of power grid properties, and reduces the size of the thermal equivalent network dramatically (only 13% of the size of the power grid). Iterative methods [16] are used to efficiently update the IR drops based on the new temperature profile. Experimental results show that without considering temperature impact, the worst IR drop analysis can have error up to 10%.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method.
{"title":"An Efficient Method for Fast Delay and SI Calculation Using Current Source Models","authors":"Xin Wang, Alireza Kasnavi, H. Levy","doi":"10.1109/ISQED.2008.69","DOIUrl":"https://doi.org/10.1109/ISQED.2008.69","url":null,"abstract":"Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131096761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new asynchronous circuit design is presented. A special technique that enables fast forwarding is applied to the circuits, and the forward transition improves to less than 2. The handshaking process and cycle time of the asynchronous circuits are analyzed, and its performance and functionality under fabrication and temperature variations are evaluated through Monte Carlo simulations in 65 nm technology. The proposed asynchronous circuits are compared to the static and domino logic circuits to assess their delay variations and functional success rates.
{"title":"An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node","authors":"Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu","doi":"10.1109/ISQED.2008.117","DOIUrl":"https://doi.org/10.1109/ISQED.2008.117","url":null,"abstract":"In this paper, a new asynchronous circuit design is presented. A special technique that enables fast forwarding is applied to the circuits, and the forward transition improves to less than 2. The handshaking process and cycle time of the asynchronous circuits are analyzed, and its performance and functionality under fabrication and temperature variations are evaluated through Monte Carlo simulations in 65 nm technology. The proposed asynchronous circuits are compared to the static and domino logic circuits to assess their delay variations and functional success rates.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131376485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As CMOS technology scales continually, interconnect power has become a significant part of total chip power. Without compromising performance, timing slacks can be utilized to optimize interconnect power efficiently. The optimization of total interconnect power is affected not only by the properties of each interconnect as well as the timing constraint, but also by the circuit topology. In this paper, we introduce a novel slack distribution algorithm IPOSA to optimize interconnect power efficiently. A piecewise linear model is proposed to quantify the relationship between interconnect power reduction and timing slack amount, considering the interconnect length and the switching activity. Monte Carlo analysis shows our piecewise model is accurate enough that the average error is 1.7%. Based on the piecewise linearity of the model, we propose an iterative slack distribution algorithm which minimizes total interconnect power with given performance constraint. The experimental results show that our algorithm can achieve 41.7% interconnect power reduction on average.
{"title":"IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization","authors":"Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong","doi":"10.1109/ISQED.2008.96","DOIUrl":"https://doi.org/10.1109/ISQED.2008.96","url":null,"abstract":"As CMOS technology scales continually, interconnect power has become a significant part of total chip power. Without compromising performance, timing slacks can be utilized to optimize interconnect power efficiently. The optimization of total interconnect power is affected not only by the properties of each interconnect as well as the timing constraint, but also by the circuit topology. In this paper, we introduce a novel slack distribution algorithm IPOSA to optimize interconnect power efficiently. A piecewise linear model is proposed to quantify the relationship between interconnect power reduction and timing slack amount, considering the interconnect length and the switching activity. Monte Carlo analysis shows our piecewise model is accurate enough that the average error is 1.7%. Based on the piecewise linearity of the model, we propose an iterative slack distribution algorithm which minimizes total interconnect power with given performance constraint. The experimental results show that our algorithm can achieve 41.7% interconnect power reduction on average.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Characteristics of the on-chip power supply noise in a 6.4 Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4 Gbps are observed in time and frequency domain.
{"title":"Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces","authors":"H. Lan, R. Schmitt, Xingchao Yuan","doi":"10.1109/ISQED.2008.25","DOIUrl":"https://doi.org/10.1109/ISQED.2008.25","url":null,"abstract":"Characteristics of the on-chip power supply noise in a 6.4 Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4 Gbps are observed in time and frequency domain.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121351336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper extends the existing synchronous dataflow (SDF) model to provide dynamic behavior and top down design with compile time deadlock detection and bounded buffer memory. We propose a new dataflow model called constant rate dataflow with intermediate ports (CRDF-IP) in which a component (or actor) can send and receive data to/from another actor through intermediate port during its execution. Since an actor can call another actor multiple times per execution, dynamic behaviors are easily specified without introducing run-time scheduler. Moreover, top-down design can be achieved by extracting a sub-actor from the top actor. This paper has proved that deadlock detection and buffer size computation can be performed at compile in CRDF-IP model. The proposed model has been implemented in a system level design platform in which H.263 video encoding algorithm is specified.
{"title":"Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior","authors":"Hyunok Oh","doi":"10.1109/ISQED.2008.138","DOIUrl":"https://doi.org/10.1109/ISQED.2008.138","url":null,"abstract":"This paper extends the existing synchronous dataflow (SDF) model to provide dynamic behavior and top down design with compile time deadlock detection and bounded buffer memory. We propose a new dataflow model called constant rate dataflow with intermediate ports (CRDF-IP) in which a component (or actor) can send and receive data to/from another actor through intermediate port during its execution. Since an actor can call another actor multiple times per execution, dynamic behaviors are easily specified without introducing run-time scheduler. Moreover, top-down design can be achieved by extracting a sub-actor from the top actor. This paper has proved that deadlock detection and buffer size computation can be performed at compile in CRDF-IP model. The proposed model has been implemented in a system level design platform in which H.263 video encoding algorithm is specified.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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