Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper presents robustness of heterogeneous multiprocessor systems to SEUs and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints.
{"title":"SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems","authors":"M. Sugihara","doi":"10.1109/ISQED.2008.126","DOIUrl":"https://doi.org/10.1109/ISQED.2008.126","url":null,"abstract":"Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper presents robustness of heterogeneous multiprocessor systems to SEUs and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132027743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a full-chip RLC crosstalk budgeting routing flow to generate a high-quality routing design under stringent crosstalk constraints. Based on the cost function addressing the sensitive nets in visited global cells for each net, global routing can lower routing congestion as well as coupling effect. Crosstalk-driven track routing minimizes capacitive coupling effects, and decreases inductive coupling effects by avoiding placing sensitive nets on adjacent tracks. To achieve inductive crosstalk budgeting optimization, the shield insertion problem can be solved with a minimum column covering algorithm, which is undertaken following track routing to process nets with an excess of inductive crosstalk. The proposed routing flow method can identify the required number of shields more accurately, and process more complex routing problems, than the linear programming (LP) methods. Results of this study demonstrate that the proposed approach can effectively and quickly lower inductive crosstalk by up to one-third.
{"title":"Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing","authors":"Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li","doi":"10.1109/ISQED.2008.88","DOIUrl":"https://doi.org/10.1109/ISQED.2008.88","url":null,"abstract":"This work presents a full-chip RLC crosstalk budgeting routing flow to generate a high-quality routing design under stringent crosstalk constraints. Based on the cost function addressing the sensitive nets in visited global cells for each net, global routing can lower routing congestion as well as coupling effect. Crosstalk-driven track routing minimizes capacitive coupling effects, and decreases inductive coupling effects by avoiding placing sensitive nets on adjacent tracks. To achieve inductive crosstalk budgeting optimization, the shield insertion problem can be solved with a minimum column covering algorithm, which is undertaken following track routing to process nets with an excess of inductive crosstalk. The proposed routing flow method can identify the required number of shields more accurately, and process more complex routing problems, than the linear programming (LP) methods. Results of this study demonstrate that the proposed approach can effectively and quickly lower inductive crosstalk by up to one-third.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133890292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Young-Gu Kim, Soo-Hwan Kim, H. Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo
Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200 MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.
{"title":"The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era","authors":"Young-Gu Kim, Soo-Hwan Kim, H. Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo","doi":"10.1109/ISQED.2008.108","DOIUrl":"https://doi.org/10.1109/ISQED.2008.108","url":null,"abstract":"Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200 MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115711485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper extends the existing synchronous dataflow (SDF) model to provide dynamic behavior and top down design with compile time deadlock detection and bounded buffer memory. We propose a new dataflow model called constant rate dataflow with intermediate ports (CRDF-IP) in which a component (or actor) can send and receive data to/from another actor through intermediate port during its execution. Since an actor can call another actor multiple times per execution, dynamic behaviors are easily specified without introducing run-time scheduler. Moreover, top-down design can be achieved by extracting a sub-actor from the top actor. This paper has proved that deadlock detection and buffer size computation can be performed at compile in CRDF-IP model. The proposed model has been implemented in a system level design platform in which H.263 video encoding algorithm is specified.
{"title":"Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior","authors":"Hyunok Oh","doi":"10.1109/ISQED.2008.138","DOIUrl":"https://doi.org/10.1109/ISQED.2008.138","url":null,"abstract":"This paper extends the existing synchronous dataflow (SDF) model to provide dynamic behavior and top down design with compile time deadlock detection and bounded buffer memory. We propose a new dataflow model called constant rate dataflow with intermediate ports (CRDF-IP) in which a component (or actor) can send and receive data to/from another actor through intermediate port during its execution. Since an actor can call another actor multiple times per execution, dynamic behaviors are easily specified without introducing run-time scheduler. Moreover, top-down design can be achieved by extracting a sub-actor from the top actor. This paper has proved that deadlock detection and buffer size computation can be performed at compile in CRDF-IP model. The proposed model has been implemented in a system level design platform in which H.263 video encoding algorithm is specified.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Characteristics of the on-chip power supply noise in a 6.4 Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4 Gbps are observed in time and frequency domain.
{"title":"Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces","authors":"H. Lan, R. Schmitt, Xingchao Yuan","doi":"10.1109/ISQED.2008.25","DOIUrl":"https://doi.org/10.1109/ISQED.2008.25","url":null,"abstract":"Characteristics of the on-chip power supply noise in a 6.4 Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4 Gbps are observed in time and frequency domain.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121351336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 4-bit flash ADC is investigated in presence of substrate noise generated by switching activities in digital blocks. The impact of noise is analyzed in different building blocks of the ADC and is measured experimentally using a high-speed ADC test block fabricated in a 0.18-mum SiGe BiCMOS process. Measurement results show that noise spikes in the substrate cause distortion in the prototype ADC and degrade its SNDR by 2 dB (10%) at noise frequencies above 200 MHz.
研究了一个4位闪存ADC在数字块中开关活动所产生的衬底噪声的存在。在ADC的不同构建模块中分析了噪声的影响，并使用以0.18 μ m SiGe BiCMOS工艺制作的高速ADC测试模块进行了实验测量。测量结果表明，在噪声频率高于200 MHz时，衬底中的噪声尖峰会导致原型ADC失真，使其SNDR降低2 dB(10%)。
{"title":"Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs","authors":"P. Nikaeen, B. Murmann, R. Dutton","doi":"10.1109/ISQED.2008.141","DOIUrl":"https://doi.org/10.1109/ISQED.2008.141","url":null,"abstract":"A 4-bit flash ADC is investigated in presence of substrate noise generated by switching activities in digital blocks. The impact of noise is analyzed in different building blocks of the ADC and is measured experimentally using a high-speed ADC test block fabricated in a 0.18-mum SiGe BiCMOS process. Measurement results show that noise spikes in the substrate cause distortion in the prototype ADC and degrade its SNDR by 2 dB (10%) at noise frequencies above 200 MHz.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124855835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Wang, K. Agarwal, S. Nassif, K. Nowka, D. Markovic
A new approach to analyze process variation through measured current variation is introduced. The methodology concludes with a simple and convenient posynomial model for random process variability to bridge the gap between existing statistical methods and circuit design. The model contains only design variables: transistor sizes W and L, and operating points Vgs and Vds. Modeling random process variability in this way allows for adaptability to optimization problems, time efficient methods for gathering statistical information in comparison to Monte Carlo, and an alternative equation for hand analysis.
{"title":"A Design Model for Random Process Variability","authors":"V. Wang, K. Agarwal, S. Nassif, K. Nowka, D. Markovic","doi":"10.1109/ISQED.2008.111","DOIUrl":"https://doi.org/10.1109/ISQED.2008.111","url":null,"abstract":"A new approach to analyze process variation through measured current variation is introduced. The methodology concludes with a simple and convenient posynomial model for random process variability to bridge the gap between existing statistical methods and circuit design. The model contains only design variables: transistor sizes W and L, and operating points Vgs and Vds. Modeling random process variability in this way allows for adaptability to optimization problems, time efficient methods for gathering statistical information in comparison to Monte Carlo, and an alternative equation for hand analysis.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124198549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to redundancy techniques. A new design technique, distinct from error detection, predicts failures before they actually create errors in system data and states. Circuit failure prediction is ideal for reliability mechanisms such as transistor aging and early-life failures, and can enable close to best-case design by minimizing traditional worst-case speed guardbands.
{"title":"Tutorial 4: Robust System Design in Scaled CMOS","authors":"S. Mitra","doi":"10.1109/ISQED.2008.175","DOIUrl":"https://doi.org/10.1109/ISQED.2008.175","url":null,"abstract":"Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to redundancy techniques. A new design technique, distinct from error detection, predicts failures before they actually create errors in system data and states. Circuit failure prediction is ideal for reliability mechanisms such as transistor aging and early-life failures, and can enable close to best-case design by minimizing traditional worst-case speed guardbands.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130301202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method.
{"title":"An Efficient Method for Fast Delay and SI Calculation Using Current Source Models","authors":"Xin Wang, Alireza Kasnavi, H. Levy","doi":"10.1109/ISQED.2008.69","DOIUrl":"https://doi.org/10.1109/ISQED.2008.69","url":null,"abstract":"Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131096761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost.
{"title":"Error Protected Data Bus Inversion Using Standard DRAM Components","authors":"M. Skerlj, P. Ienne","doi":"10.1109/ISQED.2008.74","DOIUrl":"https://doi.org/10.1109/ISQED.2008.74","url":null,"abstract":"Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"507 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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