We analyze the correlation between different parameters of the on-chip power distribution grid and their impact on noise. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. We derive the correlation between design variables and noise from an analysis of 300 different grids in a 65-nm process technology, and manage to find the impact that a change in power grid design variables will have on noise. The results from this analysis can be used as guidelines when designing a robust power distribution grid.
{"title":"Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach","authors":"D. Andersson, L. Svensson, P. Larsson-Edefors","doi":"10.1109/ISQED.2008.148","DOIUrl":"https://doi.org/10.1109/ISQED.2008.148","url":null,"abstract":"We analyze the correlation between different parameters of the on-chip power distribution grid and their impact on noise. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. We derive the correlation between design variables and noise from an analysis of 300 different grids in a 65-nm process technology, and manage to find the impact that a change in power grid design variables will have on noise. The results from this analysis can be used as guidelines when designing a robust power distribution grid.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the relative levels of coupling capacitance in smaller process geometries and of process variations caused due to lithography, CMP, and Etch process increases, process variation aware coupled noise analysis is becoming more important especially at under 45 nm design and below. We propose a method to simulate crosstalk noise for the worst process corner cases. Our method considers a spatial correlation for transistor length variations because the difference of the driver strength between victim and aggressor is the main source of the variation. Both lithography and CMP variation are first considered separately and combined to show crosstalk noise change for interconnect variations. We compare results for various process variation models using a crosstalk test structure. In these simulation studies, crosstalk noise without variation consideration underestimates by up to 17% the noise of the proposed worst corner model.
{"title":"Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner","authors":"Jae-Seok Yang, A. Neureuther","doi":"10.1109/ISQED.2008.22","DOIUrl":"https://doi.org/10.1109/ISQED.2008.22","url":null,"abstract":"As the relative levels of coupling capacitance in smaller process geometries and of process variations caused due to lithography, CMP, and Etch process increases, process variation aware coupled noise analysis is becoming more important especially at under 45 nm design and below. We propose a method to simulate crosstalk noise for the worst process corner cases. Our method considers a spatial correlation for transistor length variations because the difference of the driver strength between victim and aggressor is the main source of the variation. Both lithography and CMP variation are first considered separately and combined to show crosstalk noise change for interconnect variations. We compare results for various process variation models using a crosstalk test structure. In these simulation studies, crosstalk noise without variation consideration underestimates by up to 17% the noise of the proposed worst corner model.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115428396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability; while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM; FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible versatile processing unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.
{"title":"Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform","authors":"A. Cheng","doi":"10.1109/ISQED.2008.85","DOIUrl":"https://doi.org/10.1109/ISQED.2008.85","url":null,"abstract":"Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability; while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM; FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible versatile processing unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose an efficient statistical analysis method for analyzing on-chip power grids. The new method, called SN-SOR (and its faster version, PSN- SOR), is based on a novel localized relaxed iterative approach and it can perform variational analysis on one node at a time. PSN-SOR further speeds up the analysis by using a refined conditioner, where the initial solution of SN-SOR is used as the pre-conditioner for the later iterations. Experimental results show that PSN-SOR is about two orders of magnitude(186X) faster than Monte- Carlo method with slight errors less than 5.685% on maximum and is about one order magnitude (41X) faster than general global successive over relaxation (SOR) method. PSN-SOR is more accurate and efficient than the recently proposed random walk method for localized statistical analysis.
{"title":"Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method","authors":"Zuying Luo, S. Tan","doi":"10.1109/ISQED.2008.62","DOIUrl":"https://doi.org/10.1109/ISQED.2008.62","url":null,"abstract":"In this paper, we propose an efficient statistical analysis method for analyzing on-chip power grids. The new method, called SN-SOR (and its faster version, PSN- SOR), is based on a novel localized relaxed iterative approach and it can perform variational analysis on one node at a time. PSN-SOR further speeds up the analysis by using a refined conditioner, where the initial solution of SN-SOR is used as the pre-conditioner for the later iterations. Experimental results show that PSN-SOR is about two orders of magnitude(186X) faster than Monte- Carlo method with slight errors less than 5.685% on maximum and is about one order magnitude (41X) faster than general global successive over relaxation (SOR) method. PSN-SOR is more accurate and efficient than the recently proposed random walk method for localized statistical analysis.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122172439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to scaling down of semiconductor technology, modern deep-submicron VLSI circuits are becoming increasingly vulnerable to noise from multiple sources, including cross-talk, radiation-induced single event transient, and power supply noises. Noise Rejection Curve (NRC) has been used as a metric to model noise susceptibility of logic circuits to such sources. In this paper an analytical model for NRC, which includes short channel effects, is presented. The model uses only basic SPICE parameters and does not include any calibration parameter. Comparison with SPICE simulations using TSMC 0.25 um CMOS process parameters, suggests that the proposed model can accurately predict NRC characteristic of variety of logic circuits.
由于半导体技术的缩小，现代深亚微米VLSI电路越来越容易受到来自多个来源的噪声的影响，包括串扰、辐射诱发的单事件瞬态和电源噪声。噪声抑制曲线(NRC)已被用作一种度量来模拟逻辑电路对此类源的噪声敏感性。本文提出了考虑短信道效应的核反应堆分析模型。该模型仅使用基本SPICE参数，不包括任何校准参数。与采用台积电0.25 μ m CMOS工艺参数的SPICE仿真结果比较，表明该模型能够准确预测各种逻辑电路的NRC特性。
{"title":"Analytical Noise-Rejection Model Based on Short Channel MOSFET","authors":"V. Jain, P. Zarkesh-Ha","doi":"10.1109/ISQED.2008.166","DOIUrl":"https://doi.org/10.1109/ISQED.2008.166","url":null,"abstract":"Due to scaling down of semiconductor technology, modern deep-submicron VLSI circuits are becoming increasingly vulnerable to noise from multiple sources, including cross-talk, radiation-induced single event transient, and power supply noises. Noise Rejection Curve (NRC) has been used as a metric to model noise susceptibility of logic circuits to such sources. In this paper an analytical model for NRC, which includes short channel effects, is presented. The model uses only basic SPICE parameters and does not include any calibration parameter. Comparison with SPICE simulations using TSMC 0.25 um CMOS process parameters, suggests that the proposed model can accurately predict NRC characteristic of variety of logic circuits.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-17DOI: 10.1093/ietfec/e91-a.12.3465
Yi Wang, Xuan Zeng, J. Tao, Hengliang Zhu, Xu Luo, Changhao Yan, W. Cai
In this paper, we propose an adaptive stochastic collocation method for block-based statistical static timing analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on homogeneous chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using sparse grid technique, the proposed method has 10times improvements in the accuracy while using the same order of computation time. The proposed algorithm also show great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100times speeds up.
{"title":"Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model","authors":"Yi Wang, Xuan Zeng, J. Tao, Hengliang Zhu, Xu Luo, Changhao Yan, W. Cai","doi":"10.1093/ietfec/e91-a.12.3465","DOIUrl":"https://doi.org/10.1093/ietfec/e91-a.12.3465","url":null,"abstract":"In this paper, we propose an adaptive stochastic collocation method for block-based statistical static timing analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on homogeneous chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using sparse grid technique, the proposed method has 10times improvements in the accuracy while using the same order of computation time. The proposed algorithm also show great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100times speeds up.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. NBTI is highly sensitive to operating temperature, making the amount of degradation strongly dependent on the thermal history of the chip. In order to accurately predict the amount of threshold voltage increase, the precise temperature profile must be utilized. The existing models are based on the simplified analysis which assumes that the temperature takes up to two possible fixed values over time. These models are inaccurate when predicting the impact of continuously-changing temperature that spans a large range. Our experiments show that proposed model accounting for temperature variation provides a significantly tighter bound for the simulation than that from the model that ignores the temperature variation and assumes a constant (worst-case) temperature. In our experiment, the amount of degradation predicted by the proposed dynamic temperature model is on average 46% less conservative compared to the model based on the worst-case temperature.
{"title":"Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation","authors":"Bin Zhang, M. Orshansky","doi":"10.1109/ISQED.2008.151","DOIUrl":"https://doi.org/10.1109/ISQED.2008.151","url":null,"abstract":"Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. NBTI is highly sensitive to operating temperature, making the amount of degradation strongly dependent on the thermal history of the chip. In order to accurately predict the amount of threshold voltage increase, the precise temperature profile must be utilized. The existing models are based on the simplified analysis which assumes that the temperature takes up to two possible fixed values over time. These models are inaccurate when predicting the impact of continuously-changing temperature that spans a large range. Our experiments show that proposed model accounting for temperature variation provides a significantly tighter bound for the simulation than that from the model that ignores the temperature variation and assumes a constant (worst-case) temperature. In our experiment, the amount of degradation predicted by the proposed dynamic temperature model is on average 46% less conservative compared to the model based on the worst-case temperature.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Dabiri, Navid Amini, Mahsan Rofouei, M. Sarrafzadeh
Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic voltage scheduling (DVS) has been provably one of the most effective techniques used to achieve low power specification. On the other hand, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEUs) becomes exponentially greater. Lowering supply voltage to save energy increases soft error rates caused by SEU for two reasons: I) lower voltage makes digital circuits more prone to soft errors and II) reduction in supply voltage, increases the duration of process which increases the chances of being hit by SEU. In this paper, we propose an optimal methodology for DVS on a task graph with consideration of soft error rate. We consider the effects of voltage on SEU and incorporate this dependency in our formulation to develop a new method for energy optimization under SEU constraints. We also propose a convex programming formulation that can be solved efficiently and optimally. We show the effectiveness of our optimal results by simulation on TGFF benchmarks.
{"title":"Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems","authors":"F. Dabiri, Navid Amini, Mahsan Rofouei, M. Sarrafzadeh","doi":"10.1109/ISQED.2008.161","DOIUrl":"https://doi.org/10.1109/ISQED.2008.161","url":null,"abstract":"Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic voltage scheduling (DVS) has been provably one of the most effective techniques used to achieve low power specification. On the other hand, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEUs) becomes exponentially greater. Lowering supply voltage to save energy increases soft error rates caused by SEU for two reasons: I) lower voltage makes digital circuits more prone to soft errors and II) reduction in supply voltage, increases the duration of process which increases the chances of being hit by SEU. In this paper, we propose an optimal methodology for DVS on a task graph with consideration of soft error rate. We consider the effects of voltage on SEU and incorporate this dependency in our formulation to develop a new method for energy optimization under SEU constraints. We also propose a convex programming formulation that can be solved efficiently and optimally. We show the effectiveness of our optimal results by simulation on TGFF benchmarks.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper illustrates the application of distributional robustness theory to compute the worst-case timing yield of a circuit. Our assumption is that the probability distribution of process variables are unknown and only the intervals of the process variables and their class of distributions are available. We consider two practical classes to group potential distributions. We then derive conditions that allow applying the results of the distributional robustness theory to efficiently and accurately estimate the worst-case timing yield for each class. Compared to other recent works, our approach can model correlations among process variables and does not require knowledge of exact function form of the joint distribution function of process variables. While our emphasis is on robust timing yield estimation, our approach is also applicable to other types of parametric yield.
{"title":"Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations","authors":"Lin Xie, A. Davoodi","doi":"10.1109/ISQED.2008.104","DOIUrl":"https://doi.org/10.1109/ISQED.2008.104","url":null,"abstract":"This paper illustrates the application of distributional robustness theory to compute the worst-case timing yield of a circuit. Our assumption is that the probability distribution of process variables are unknown and only the intervals of the process variables and their class of distributions are available. We consider two practical classes to group potential distributions. We then derive conditions that allow applying the results of the distributional robustness theory to efficiently and accurately estimate the worst-case timing yield for each class. Compared to other recent works, our approach can model correlations among process variables and does not require knowledge of exact function form of the joint distribution function of process variables. While our emphasis is on robust timing yield estimation, our approach is also applicable to other types of parametric yield.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125539139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backdrop, the interaction of high-k/metal gates with end of roadmap devices would be thoroughly explored. High-k/metal gates have interesting ramifications in the circuit space-from NBTI (negative bias temperature instability) to high-field mobility, the high-k gate induced physical phenomena and their impact on device and circuit performance and reliability would be discussed. To conclude, this talk would also conjecture on the continued scalability of high-k gate stacks for futuristic CMOS device architectures.
{"title":"Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications","authors":"K. Maitra","doi":"10.1109/ISQED.2008.172","DOIUrl":"https://doi.org/10.1109/ISQED.2008.172","url":null,"abstract":"Summary form only given. Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backdrop, the interaction of high-k/metal gates with end of roadmap devices would be thoroughly explored. High-k/metal gates have interesting ramifications in the circuit space-from NBTI (negative bias temperature instability) to high-field mobility, the high-k gate induced physical phenomena and their impact on device and circuit performance and reliability would be discussed. To conclude, this talk would also conjecture on the continued scalability of high-k gate stacks for futuristic CMOS device architectures.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：